代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/309046/3707938
scr run_sim.scr
#!/bin/csh -f
# GLOBAL VARIABLES
###################
set sim_top = testbench;
set arg_tool = "NCSim"; # By default NCSim is used as simulation tool
set arg_wave = 0; # By defa
www.eeworm.com/read/354886/3072521
scr run_sim.scr
#!/bin/csh -f
# GLOBAL VARIABLES
###################
set sim_top = testbench;
set arg_tool = "NCSim"; # By default NCSim is used as simulation tool
set arg_wave = 0; # By defa
www.eeworm.com/read/402457/6786108
tf turboencodertest.tf
`timescale 1ns/1ns
module testbench();
// DATE: Thu Dec 09 10:32:08 2004
// TITLE:
// MODULE: turboencoder
// DESIGN: turboencoder
// FILENAME: turboencoder
// PROJECT: turbo
www.eeworm.com/read/368409/9697017
tf cnt99_tb.tf
module testbench();
// Inputs
reg clk;
reg reset;
// Outputs
wire [3:0] one_out;
wire [3:0] ten_out;
// Instantiate the UUT
counter uut (
.clk(clk),
www.eeworm.com/read/384728/8849508
vhd 33_simu.vhd
-- Author : yzf
-- Created On: Thu Dec 21 09:46:16 1995
-- Testbench for comp.comp
architecture BENCH of test_comp is
component comp
PORT(
A: IN SHORT;
B: IN SHORT;
IN_READY:
www.eeworm.com/read/284185/8956263
vhd 33_simu.vhd
-- Author : yzf
-- Created On: Thu Dec 21 09:46:16 1995
-- Testbench for comp.comp
architecture BENCH of test_comp is
component comp
PORT(
A: IN SHORT;
B: IN SHORT;
IN_READY:
www.eeworm.com/read/183822/9136241
makefile
#
# Phelix testbench makefile
#
!if defined(ECRYPT_API) || defined(ECRYPT)
_DEFINES_ = -DECRYPT_API
_CIPHER_ = "ECRYPT-Phelix"
_TASMDEF_ = -TDECRYPT_API # pass along the swi
www.eeworm.com/read/366182/9826137
vhd 33_simu.vhd
-- Author : yzf
-- Created On: Thu Dec 21 09:46:16 1995
-- Testbench for comp.comp
architecture BENCH of test_comp is
component comp
PORT(
A: IN SHORT;
B: IN SHORT;
IN_READY:
www.eeworm.com/read/364127/9921624
v fsm_example_tb.v
//===== Finite State Machine Example =====
//----- Testbench -----
// Timescale: one time unit = 1ns (e.g., delay specification of #42 means 42ns of time), and
// simulator resolution is 0.1 ns
www.eeworm.com/read/364127/9921632
v fsm_example2_tb.v
//===== Finite State Machine Example =====
//----- Testbench -----
// Timescale: one time unit = 1ns (e.g., delay specification of #42 means 42ns of time), and
// simulator resolution is 0.1 ns