turboencodertest.tf

turbo码_verilog_编码源文件

 `timescale 1ns/1ns

module testbench();

// DATE:     Thu Dec 09 10:32:08 2004 
// TITLE:    
// MODULE:   turboencoder
// DESIGN:   turboencoder
// FILENAME: turboencoder
// PROJECT:  turbo_encoder
// VERSION:  Version


// Inputs
    reg reset_n;
    reg data_clk;
    reg framehead;
    reg bitin;


// Outputs
    wire syscodeout;
    wire paricodeout;
    wire turboencoder_over;
	 //for test:
	// wire  interbitout;
 //wire  interleaver_over;
 //wire  sysbitout1;
 //wire paribitout1;
 //wire sysbitout2;
 //wire paribitout2;
 //wire rscencoder_over;
 //wire tailouten;

// Bidirs


// Instantiate the UUT
    turboencoder uut (
        .reset_n(reset_n), 
        .data_clk(data_clk), 
        .framehead(framehead), 
        .bitin(bitin), 
        .syscodeout(syscodeout), 
        .paricodeout(paricodeout), 
        .turboencoder_over(turboencoder_over)
		  //for test:
		  //.interbitout(interbitout),
         //.interleaver_over(interleaver_over),
         //.sysbitout1(sysbitout1),
         //.paribitout1(paribitout1),
         //.sysbitout2(sysbitout2),
         //.paribitout2(paribitout2),
         //.rscencoder_over(rscencoder_over),
         //.tailouten (tailouten)
        );

 always
begin
 #8 data_clk=1;
 #48 data_clk=0;
 #40 data_clk=0;
end

integer i;
integer fsysout;
integer fpariout;
reg din [0:4091];
reg [12:0] count4096;

// Initialize Inputs
    //`ifdef auto_init

        initial begin
            reset_n = 0;
            data_clk = 0;
            framehead = 0;
            bitin = 0;
				#56 reset_n=1;
				#96 reset_n=0;
				i=0;
				#58 framehead=1;
			   $readmemb("e:/turbo/mfile/float_simulation/test2/msg_verilog.txt",din,0,4091);
            fsysout=$fopen("e:/turbo/mfile/float_simulation/test2/syscode_verilog.txt");
				fpariout=$fopen("e:/turbo/mfile/float_simulation/test2/paricode_verilog.txt");
				#96 framehead=0;
				//#393120  framehead=1;
				#96 framehead=0;
				#1000000 $stop;
				$fclose(fsysout);
				$fclose(fpariout);
        end

    //`endif

always@(posedge data_clk)
if(framehead)
repeat(4096)
begin
#10
bitin<=din[i];
i<=i+1;
#86;
end

always@(posedge data_clk)
if(reset_n)
  count4096<=13'd4096;
else if(turboencoder_over)
     count4096<=0;
	  else if(!count4096[12]) 
	  count4096<=count4096+1;


always@(posedge data_clk)
begin
 if(!count4096[12])
 $fwrite(fsysout,"%b\n",syscodeout);
end

always@(posedge data_clk)
begin
 if(!count4096[12])
 $fwrite(fpariout,"%b\n",paricodeout);
end

endmodule