代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/360253/10105546
do wave.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /testbench/test_controller/clk
add wave -noupdate -format Logic /testbench/test_controller/reset
add wave -noupd
www.eeworm.com/read/281220/10255790
do wave_func.do
onerror {resume}
quietly WaveActivateNextPane {} 0
quietly virtual signal -install /testbench/cf_plus_top/cf_plus_logic/attribute_memory_array { (context /testbench/cf_plus_top/cf_plus_logic/attribu
www.eeworm.com/read/423217/10578990
_deps
H 2141964 10 1 0 3 3 0 0 0 0
L 4 work 4 work
D 13 work.receiver
www.eeworm.com/read/462922/7191605
do sim.do
#退出上一次仿真
quit -sim
#建立work库
vlib work
#把ModelSim所要使用的work库映射到新建立的work库上
vmap work work
#编译Altera的仿真库文件
vlog altera_mf.v
#编译设计文件
vlog DualPortRAM.v
#编译顶层文件
vlog TOP.v
#编译testben
www.eeworm.com/read/452779/7433117
v ex_111_tb.v
`timescale 1 ns/1 ns
module testbench;
reg [7:0] a, b, c;
wire [15:0] k_usgn, k_sgn;
EX_111_bit_manipulation EX111_instance(
.a(a),
.b(b),
.c(c),
.k_usgn(k_usgn),
.k_sgn(k_sgn)
www.eeworm.com/read/447390/7553635
vhd tbw.vhd
-- VHDL Test Bench Created from source file fenpin1.vhd -- 16:23:39 09/20/2008
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for
www.eeworm.com/read/246855/12700690
do post_sim.do
vlib work
vcom -just e -87 -explicit -work work uc_interface_timesim.vhd
vcom -skip e -87 -explicit -work work uc_interface_timesim.vhd
vcom -just e -93 -explicit -work work uc_interface_tb.vhd
www.eeworm.com/read/321786/13399262
do sim.do
#退出上一次仿真
quit -sim
#建立work库
vlib work
#把ModelSim所要使用的work库映射到新建立的work库上
vmap work work
#编译Altera的仿真库文件
vlog altera_mf.v
#编译设计文件
vlog DualPortRAM.v
#编译顶层文件
vlog TOP.v
#编译testben
www.eeworm.com/read/321786/13399268
do sim.do
#退出上一次仿真
quit -sim
#建立work库
vlib work
#把ModelSim所要使用的work库映射到新建立的work库上
vmap work work
#编译Altera的仿真库文件
vlog altera_mf.v
#编译设计文件
vlog DualPortRAM.v
#编译顶层文件
vlog TOP.v
#编译testben
www.eeworm.com/read/306496/13743582
vcd dump.vcd
$date
Mon Jul 24 20:52:49 2006
$end
$version
Icarus Verilog
$end
$timescale
10ps
$end
$scope module testbench $end
$var reg 1 ! clk $end
$var reg 4 " ins_len[3:0] $end
$var reg 8 # ip_n