ex_111_tb.v

来自「unsigned and signed multiply circuit imp」· Verilog 代码 · 共 24 行

`timescale 1 ns/1 ns

module testbench;
reg	[7:0]	a, b, c;
wire	[15:0]	k_usgn, k_sgn;

EX_111_bit_manipulation EX111_instance(
		.a(a),
		.b(b),
		.c(c),
		.k_usgn(k_usgn),
		.k_sgn(k_sgn) );
initial
begin
 a   = 8'h35;	// Time = 0
 b   = 8'h76;
 c   = 8'h9a;
 #50;		// Time = 50
 a   = 8'h18;
 b   = 8'h86;
 c   = 8'h51;
end
endmodule