代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/215972/15031610
tf testbench.tf
`timescale 1ns/1ns
module testbench;
wire Gold_Code_T;
reg Clock_T;
reg Enable_T;
reg Fill_En_A_T;
reg Fill_En_B_T;
reg New_Fill_A_T;
reg New_Fill_B_T;
gold_code U0 (.Clock(Clock_T), .Fill_En_A(Fil
www.eeworm.com/read/18458/789713
udo testbench.udo
## Project Navigator Verilog simulation template: testbench.udo
## You may edit this file to control your simulation.
www.eeworm.com/read/18458/789741
tf testbench.tf
`timescale 1ns/10ps
module testbench();
reg reset;
reg clk;
wire[31:0] counter;
initial
begin
reset=1;
clk=0;
#5 reset=0;
#5 reset=1;
#10000000 $stop;
end
always #50 clk=~clk;
www.eeworm.com/read/18458/789797
udo testbench.udo
## Project Navigator Verilog simulation template: testbench.udo
## You may edit this file to control your simulation.
www.eeworm.com/read/18458/789829
tf testbench.tf
`timescale 1ns/10ps
module testbench();
reg reset;
reg clk;
wire[31:0] counter;
initial
begin
reset=1;
clk=0;
#5 reset=0;
#5 reset=1;
#10000000 $stop;
end
always #50 clk=~clk;
www.eeworm.com/read/18458/789833
tdo testbench.tdo
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Verilog Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module prescale_counter
vlog -93 +libext+.v+.ve+
www.eeworm.com/read/18631/798101
fdo testbench.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jul 05 18:06:28 中国标准时间 2005
##
vlib work
vcom -93 -explicit cosfunc_test.vhd
vcom -93 -explicit test2.vhd
vsi
www.eeworm.com/read/18631/798143
udo testbench.udo
-- ProjNav VHDL simulation template: testbench.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
www.eeworm.com/read/492594/1172950
v testbench.v
//////////////////////////////////////////////////////////////////////
// Created by Actel SmartDesign Mon Mar 09 09:36:32 2009
//////////////////////////////////////////////////////////////////////