testbench.tdo

来自「FPGA-CPLD_DesignTool(example7）」· TDO 代码 · 共 18 行

## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Verilog Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module prescale_counter
vlog -93 +libext+.v+.ve+ +define+OVI_Verilog+  C:/Xilinx/verilog/src/glbl.v
vlog -93 +libext+.v+.ve+ +define+OVI_Verilog+  prescale_counter_timesim.v
vlog -93  testbench.tf
vsim -t 1ps +maxdelays -L simprims_ver  -lib work testbench glbl
do testbench.udo
view wave
add wave *
add wave /glbl/GSR
view structure
view signals
run 1000ns
## End