testbench.tf

FPGA-CPLD_DesignTool(example7）

`timescale 1ns/10ps
module testbench();
reg reset;
reg clk;
wire[31:0] counter;

initial
begin
	reset=1;
	clk=0;
	#5 reset=0;
	#5 reset=1;
	#10000000  $stop;
end

always #50 clk=~clk;

reg GSR; 
assign glbl.GSR = GSR; 
reg GTS; 
assign glbl.GTS = GTS; 

initial begin 
GSR = 1; GTS = 1; 
#100 GSR = 0; GTS = 0; 			   

end

initial begin
$dumpfile("invchn26.vcd"); // Change filename as appropriate. 
$dumpvars(1, testbench.inst); 
end



prescale_counter inst(.reset(reset),.clk(clk),.counter(counter));

endmodule