代码搜索：sync

找到约 6,244 项符合「sync」的源代码

代码结果 6,244
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/402480/2321631

asm powerpc64.asm

START_FILE TEXT ALIGN(4) START_FUNC(opal_atomic_mb) sync blr END_FUNC(opal_atomic_mb) START_FUNC(opal_atomic_rmb) lwsync blr END_FUNC(opal_atomic_rmb) START_FUNC(opal_atomic_wmb) eieio bl
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www.eeworm.com/read/395929/2427230

v benif_net_wrapper.v

module BENIF_NET_WRAPPER(IFCLK, WRITE_STROBE, READ_STROBE, DMA_ENABLE, DMA_DIRECTION, DMA_RDY, DMA_DATA_AVAILABLE, RST, SYNC_RESET, DMA_RESET, ADDRESS, DATA, DMA_DATA, COUNT, DMA_SEL, DMA_WEN, DMA_REN
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www.eeworm.com/read/395929/2427267

v benif_net.v

module BENIF_NET(MIPSCLK, IFCLK, WRITE_STROBE, READ_STROBE, DMA_ENABLE, DMA_DIRECTION, DMA_RDY, DMA_DATA_AVAILABLE, RST, SYNC_RESET, DMA_RESET, ADDRESS, DATA, DMA_DATA, COUNT, DMA_SEL, DMA_WEN, DMA_RE
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www.eeworm.com/read/384663/8852897

tdf sld_ela_trigger_s5p.tdf

--sld_ela_trigger ASYNC_ENABLED=0 DATA_BITS=10 LEVEL_NAMES="sld_reserved_RVDK_Sample_auto_signaltap_0_1," SYNC_ENABLED=1 TRIGGER_LEVEL=1 acq_clk clrn data_in enable_trigger reset_all setup_bit_in setu
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www.eeworm.com/read/384663/8853028

tdf sld_ela_trigger_06p.tdf

--sld_ela_trigger ASYNC_ENABLED=0 DATA_BITS=23 LEVEL_NAMES="sld_reserved_RVDK_Sample_auto_signaltap_0_1," SYNC_ENABLED=1 TRIGGER_LEVEL=1 acq_clk clrn data_in enable_trigger reset_all setup_bit_in setu
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www.eeworm.com/read/384663/8853145

tdf sld_ela_trigger_b6p.tdf

--sld_ela_trigger ASYNC_ENABLED=0 DATA_BITS=79 LEVEL_NAMES="sld_reserved_RVDK_Sample_auto_signaltap_0_1," SYNC_ENABLED=1 TRIGGER_LEVEL=1 acq_clk clrn data_in enable_trigger reset_all setup_bit_in setu
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www.eeworm.com/read/384663/8853389

tdf sld_ela_trigger_96p.tdf

--sld_ela_trigger ASYNC_ENABLED=0 DATA_BITS=86 LEVEL_NAMES="sld_reserved_RVDK_Sample_auto_signaltap_0_1," SYNC_ENABLED=1 TRIGGER_LEVEL=1 acq_clk clrn data_in enable_trigger reset_all setup_bit_in setu
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www.eeworm.com/read/384663/8853794

tdf sld_ela_trigger_v5p.tdf

--sld_ela_trigger ASYNC_ENABLED=0 DATA_BITS=13 LEVEL_NAMES="sld_reserved_RVDK_Sample_auto_signaltap_0_1," SYNC_ENABLED=1 TRIGGER_LEVEL=1 acq_clk clrn data_in enable_trigger reset_all setup_bit_in setu
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www.eeworm.com/read/384663/8853955

tdf sld_ela_trigger_46p.tdf

--sld_ela_trigger ASYNC_ENABLED=0 DATA_BITS=81 LEVEL_NAMES="sld_reserved_RVDK_Sample_auto_signaltap_0_1," SYNC_ENABLED=1 TRIGGER_LEVEL=1 acq_clk clrn data_in enable_trigger reset_all setup_bit_in setu
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www.eeworm.com/read/426936/8990851

c usart3_step_lcd.c

#include #include #include #include #include #define SYNC 0x40 #define PARITY_EVEN 0x30 #define PARITY_ODD 0x30 #define S
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