benif_net_wrapper.v

基于4个mips核的noc设计

module BENIF_NET_WRAPPER(IFCLK, WRITE_STROBE, READ_STROBE, DMA_ENABLE, DMA_DIRECTION, DMA_RDY, DMA_DATA_AVAILABLE, RST, SYNC_RESET, DMA_RESET, ADDRESS, DATA, DMA_DATA, COUNT, DMA_SEL, DMA_WEN, DMA_REN, INT, LEDS, memADDR, memDI, memEN, memCLK, memRST, ramDO0, romDO0, ramDO1, romDO1, ramDO2, romDO2, ramDO3, romDO3, ramWE0, romWE0, ramWE1, romWE1, ramWE2, romWE2, ramWE3, romWE3, pc0, pc1, pc2, pc3, enable0, enable1, enable2, enable3, reset);
    input IFCLK;
    wire IFCLK;
    input WRITE_STROBE;
    wire WRITE_STROBE;
    input READ_STROBE;
    wire READ_STROBE;
    input DMA_ENABLE;
    wire DMA_ENABLE;
    input DMA_DIRECTION;
    wire DMA_DIRECTION;
    input DMA_RDY;
    wire DMA_RDY;
    input DMA_DATA_AVAILABLE;
    wire DMA_DATA_AVAILABLE;
    input RST;
    wire RST;
    input SYNC_RESET;
    wire SYNC_RESET;
    input DMA_RESET;
    wire DMA_RESET;
    input [30:0] ADDRESS;
    wire [30:0] ADDRESS;
    output [31:0] DATA;
    tri [31:0] DATA;
    reg [31:0] DATA;
    output [31:0] DMA_DATA;
    tri [31:0] DMA_DATA;
    reg [31:0] DMA_DATA;
    input [31:0] COUNT;
    wire [31:0] COUNT;
    input [3:0] DMA_SEL;
    wire [3:0] DMA_SEL;
    output DMA_WEN;
    reg DMA_WEN;
    output DMA_REN;
    reg DMA_REN;
    output INT;
    reg INT;
    output [3:0] LEDS;
    reg [3:0] LEDS;
    output [31:0] memADDR;
    reg [31:0] memADDR;
    output signed  [31:0] memDI;
    reg signed [31:0] memDI;
    output memEN;
    reg memEN;
    output memCLK;
    reg memCLK;
    output memRST;
    reg memRST;
    input signed  [31:0] ramDO0;
    wire signed [31:0] ramDO0;
    input signed  [31:0] romDO0;
    wire signed [31:0] romDO0;
    input signed  [31:0] ramDO1;
    wire signed [31:0] ramDO1;
    input signed  [31:0] romDO1;
    wire signed [31:0] romDO1;
    input signed  [31:0] ramDO2;
    wire signed [31:0] ramDO2;
    input signed  [31:0] romDO2;
    wire signed [31:0] romDO2;
    input signed  [31:0] ramDO3;
    wire signed [31:0] ramDO3;
    input signed  [31:0] romDO3;
    wire signed [31:0] romDO3;
    output ramWE0;
    reg ramWE0;
    output romWE0;
    reg romWE0;
    output ramWE1;
    reg ramWE1;
    output romWE1;
    reg romWE1;
    output ramWE2;
    reg ramWE2;
    output romWE2;
    reg romWE2;
    output ramWE3;
    reg ramWE3;
    output romWE3;
    reg romWE3;
    input [31:0] pc0;
    wire [31:0] pc0;
    input [31:0] pc1;
    wire [31:0] pc1;
    input [31:0] pc2;
    wire [31:0] pc2;
    input [31:0] pc3;
    wire [31:0] pc3;
    output enable0;
    reg enable0;
    output enable1;
    reg enable1;
    output enable2;
    reg enable2;
    output enable3;
    reg enable3;
    output reset;
    reg reset;
    reg [24:0] cnt;
    reg [7:0] reg__21;
    reg [31:0] addr;
    reg [31:0] memsel;
    reg [31:0] control;
    reg [7:0] reg__1;
    reg [31:0] mem;
    reg [31:0] z32;
    reg signed [6:0] i__loop_34;
    reg signed [31:0] i;
    reg signed [31:0] memout;
    reg [31:0] dout;
    reg [3:0] leds;
    reg [7:0] reg__2;
    reg en;
    reg we;
    
    always @(posedge IFCLK or posedge RST)
        begin : count
            if (RST)
                cnt <= 25'b0000000000000000000000000;
            else
                cnt <= 25'b0000000000000000000000001 + cnt;
        end

    
    always @(posedge IFCLK or posedge RST)
        begin : register_write
            if (RST)
            begin
                reg__21 = ADDRESS[7:0];
                addr <= 32'b00000000000000000000000000000000;
                memsel <= 32'b00000000000000000000000000000000;
                control <= 32'b00000000000000000000000000000000;
                if ((READ_STROBE || WRITE_STROBE) && reg__21 == 8'b00000101)
                    addr <= 32'b00000000000000000000000000000100 + addr;
            end
            else
            begin
                reg__21 = ADDRESS[7:0];
                if (WRITE_STROBE)
                    case (reg__21) //synopsys parallel_case
                    2:                      memsel <= DATA;
                    3:                      addr <= DATA;
                    4:                      control <= DATA;
                    default : begin 
                        end
                    endcase
                if ((READ_STROBE || WRITE_STROBE) && reg__21 == 8'b00000101)
                    addr <= 32'b00000000000000000000000000000100 + addr;
            end
        end

    
    always @(READ_STROBE or ADDRESS or addr or memsel or pc0 or pc1 or pc2 or pc3 or ramDO0 or romDO0 or ramDO1 or romDO1 or ramDO2 or romDO2 or ramDO3 or romDO3)
        begin : register_read
            reg__1 = ADDRESS[7:0];
            mem = memsel;
            for (i__loop_34 = 7'sb0000000 ; i__loop_34 < 7'sb0100000 ; i__loop_34 = 7'sb0000001 + i__loop_34)
                        z32[i__loop_34] = 1'bz;
            i = i__loop_34;
            case (mem) //synopsys parallel_case
            1:              memout = romDO0;
            2:              memout = ramDO0;
            4:              memout = romDO1;
            8:              memout = ramDO1;
            16:              memout = romDO2;
            32:              memout = ramDO2;
            64:              memout = romDO3;
            128:              memout = ramDO3;
            default : begin 
                memout = 0;
                end
            endcase
            case (reg__1) //synopsys parallel_case
            2:              dout = memsel;
            3:              dout = addr;
            4:              dout = control;
            5:              dout = memout;
            6:              dout = pc0;
            7:              dout = pc1;
            8:              dout = pc2;
            9:              dout = pc3;
            default : begin 
                dout = memout;
                end
            endcase
            if (READ_STROBE)
                DATA = dout;
            else
                DATA = z32;
            DMA_DATA = z32;
        end

    
    always @(IFCLK or WRITE_STROBE or READ_STROBE or DMA_ENABLE or DMA_DIRECTION or DMA_RDY or DMA_DATA_AVAILABLE or RST or SYNC_RESET or DMA_RESET or ADDRESS or DATA or DMA_DATA or COUNT or DMA_SEL or control or addr or memsel or cnt)
        begin : logic
            reset = RST;
            enable0 = control[5'b00000] != 0;
            enable1 = control[5'b00001] != 0;
            enable2 = control[5'b00010] != 0;
            enable3 = control[5'b00011] != 0;
            leds[2'b11] = !(control[5'b00000] != 0);
            leds[2'b10] = !(cnt[5'b11000] != 0);
            leds[2'b01] = 1;
            leds[2'b00] = 1;
            LEDS = leds;
            INT = 0;
            DMA_REN = 0;
            DMA_WEN = 0;
        end

    
    always @(IFCLK or DATA or addr or memsel or ADDRESS or WRITE_STROBE or control)
        begin : memory_input
            reg__2 = ADDRESS[7:0];
            en = reg__2 == 8'b00000101;
            we = en && WRITE_STROBE;
            memDI = DATA;
            romWE0 = we && memsel[5'b00000];
            ramWE0 = we && memsel[5'b00001];
            romWE1 = we && memsel[5'b00010];
            ramWE1 = we && memsel[5'b00011];
            romWE2 = we && memsel[5'b00100];
            ramWE2 = we && memsel[5'b00101];
            romWE3 = we && memsel[5'b00110];
            ramWE3 = we && memsel[5'b00111];
            memADDR = addr;
            memCLK = IFCLK;
            memEN = en;
            memRST = 0;
        end

endmodule