benif_net.v

基于4个mips核的noc设计

module BENIF_NET(MIPSCLK, IFCLK, WRITE_STROBE, READ_STROBE, DMA_ENABLE, DMA_DIRECTION, DMA_RDY, DMA_DATA_AVAILABLE, RST, SYNC_RESET, DMA_RESET, ADDRESS, DATA, DMA_DATA, COUNT, DMA_SEL, DMA_WEN, DMA_REN, INT, LEDS);
    input MIPSCLK;
    wire MIPSCLK;
    input IFCLK;
    wire IFCLK;
    input WRITE_STROBE;
    wire WRITE_STROBE;
    input READ_STROBE;
    wire READ_STROBE;
    input DMA_ENABLE;
    wire DMA_ENABLE;
    input DMA_DIRECTION;
    wire DMA_DIRECTION;
    input DMA_RDY;
    wire DMA_RDY;
    input DMA_DATA_AVAILABLE;
    wire DMA_DATA_AVAILABLE;
    input RST;
    wire RST;
    input SYNC_RESET;
    wire SYNC_RESET;
    input DMA_RESET;
    wire DMA_RESET;
    input [30:0] ADDRESS;
    wire [30:0] ADDRESS;
    output [31:0] DATA;
    output [31:0] DMA_DATA;
    input [31:0] COUNT;
    wire [31:0] COUNT;
    input [3:0] DMA_SEL;
    wire [3:0] DMA_SEL;
    output DMA_WEN;
    output DMA_REN;
    output INT;
    output [3:0] LEDS;
    wire [31:0] memADDR;
    wire signed [31:0] memDI;
    wire memEN;
    wire memCLK;
    wire memRST;
    wire signed [31:0] ramDO0;
    wire signed [31:0] romDO0;
    wire signed [31:0] ramDO1;
    wire signed [31:0] romDO1;
    wire signed [31:0] ramDO2;
    wire signed [31:0] romDO2;
    wire signed [31:0] ramDO3;
    wire signed [31:0] romDO3;
    wire ramWE0;
    wire romWE0;
    wire ramWE1;
    wire romWE1;
    wire ramWE2;
    wire romWE2;
    wire ramWE3;
    wire romWE3;
    wire [31:0] pc0;
    wire [31:0] pc1;
    wire [31:0] pc2;
    wire [31:0] pc3;
    wire enable0;
    wire enable1;
    wire enable2;
    wire enable3;
    wire reset;
    wire [17:0] x1y1dout;
    wire x1y1req_dp;
    wire x1y1ack_net;
    wire [17:0] x1y1din;
    wire x1y1req_net;
    wire x1y1ack_dp;
    wire [17:0] x0y1dout;
    wire x0y1req_dp;
    wire x0y1ack_net;
    wire [17:0] x0y1din;
    wire x0y1req_net;
    wire x0y1ack_dp;
    wire [17:0] x1y0dout;
    wire x1y0req_dp;
    wire x1y0ack_net;
    wire [17:0] x1y0din;
    wire x1y0req_net;
    wire x1y0ack_dp;
    wire [17:0] x0y0dout;
    wire x0y0req_dp;
    wire x0y0ack_net;
    wire [17:0] x0y0din;
    wire x0y0req_net;
    wire x0y0ack_dp;
    BENIF_NET_WRAPPER wrapper(.IFCLK(IFCLK), .WRITE_STROBE(WRITE_STROBE), .READ_STROBE(READ_STROBE), .DMA_ENABLE(DMA_ENABLE), .DMA_DIRECTION(DMA_DIRECTION), .DMA_RDY(DMA_RDY), .DMA_DATA_AVAILABLE(DMA_DATA_AVAILABLE), .RST(RST), .SYNC_RESET(SYNC_RESET), .DMA_RESET(DMA_RESET), .ADDRESS(ADDRESS), .DATA(DATA), .DMA_DATA(DMA_DATA), .COUNT(COUNT), .DMA_SEL(DMA_SEL), .DMA_WEN(DMA_WEN), .DMA_REN(DMA_REN), .INT(INT), .LEDS(LEDS), .memADDR(memADDR), .memDI(memDI), .memEN(memEN), .memCLK(memCLK), .memRST(memRST), .ramDO0(ramDO0), .romDO0(romDO0), .ramDO1(ramDO1), .romDO1(romDO1), .ramDO2(ramDO2), .romDO2(romDO2), .ramDO3(ramDO3), .romDO3(romDO3), .ramWE0(ramWE0), .romWE0(romWE0), .ramWE1(ramWE1), .romWE1(romWE1), .ramWE2(ramWE2), .romWE2(romWE2), .ramWE3(ramWE3), .romWE3(romWE3), .pc0(pc0), .pc1(pc1), .pc2(pc2), .pc3(pc3), .enable0(enable0), .enable1(enable1), .enable2(enable2), .enable3(enable3), .reset(reset));
    NETmMIPS dp_x1y1(.clock(MIPSCLK), .enable(enable3), .reset(reset), .data_in(x1y1dout), .req_in(x1y1req_dp), .ack_in(x1y1ack_net), .data_out(x1y1din), .req_out(x1y1req_net), .ack_out(x1y1ack_dp), .bus_pc(pc3), .ramDO(ramDO3), .ramADDR(memADDR), .ramDI(memDI), .ramEN(memEN), .ramCLK(memCLK), .ramWE(ramWE3), .ramRST(memRST), .romDO(romDO3), .romADDR(memADDR), .romDI(memDI), .romEN(memEN), .romCLK(memCLK), .romWE(romWE3), .romRST(memRST));
    NETmMIPS dp_x0y1(.clock(MIPSCLK), .enable(enable2), .reset(reset), .data_in(x0y1dout), .req_in(x0y1req_dp), .ack_in(x0y1ack_net), .data_out(x0y1din), .req_out(x0y1req_net), .ack_out(x0y1ack_dp), .bus_pc(pc2), .ramDO(ramDO2), .ramADDR(memADDR), .ramDI(memDI), .ramEN(memEN), .ramCLK(memCLK), .ramWE(ramWE2), .ramRST(memRST), .romDO(romDO2), .romADDR(memADDR), .romDI(memDI), .romEN(memEN), .romCLK(memCLK), .romWE(romWE2), .romRST(memRST));
    NETmMIPS dp_x1y0(.clock(MIPSCLK), .enable(enable1), .reset(reset), .data_in(x1y0dout), .req_in(x1y0req_dp), .ack_in(x1y0ack_net), .data_out(x1y0din), .req_out(x1y0req_net), .ack_out(x1y0ack_dp), .bus_pc(pc1), .ramDO(ramDO1), .ramADDR(memADDR), .ramDI(memDI), .ramEN(memEN), .ramCLK(memCLK), .ramWE(ramWE1), .ramRST(memRST), .romDO(romDO1), .romADDR(memADDR), .romDI(memDI), .romEN(memEN), .romCLK(memCLK), .romWE(romWE1), .romRST(memRST));
    NETmMIPS dp_x0y0(.clock(MIPSCLK), .enable(enable0), .reset(reset), .data_in(x0y0dout), .req_in(x0y0req_dp), .ack_in(x0y0ack_net), .data_out(x0y0din), .req_out(x0y0req_net), .ack_out(x0y0ack_dp), .bus_pc(pc0), .ramDO(ramDO0), .ramADDR(memADDR), .ramDI(memDI), .ramEN(memEN), .ramCLK(memCLK), .ramWE(ramWE0), .ramRST(memRST), .romDO(romDO0), .romADDR(memADDR), .romDI(memDI), .romEN(memEN), .romCLK(memCLK), .romWE(romWE0), .romRST(memRST));
    NETWORK2x2 network2x2(.clk(MIPSCLK), .rst(reset), .x0y0din(x0y0din), .x0y0dout(x0y0dout), .x0y0req_net(x0y0req_net), .x0y0ack_net(x0y0ack_net), .x0y0ack_dp(x0y0ack_dp), .x0y0req_dp(x0y0req_dp), .x0y1din(x0y1din), .x0y1dout(x0y1dout), .x0y1req_net(x0y1req_net), .x0y1ack_net(x0y1ack_net), .x0y1ack_dp(x0y1ack_dp), .x0y1req_dp(x0y1req_dp), .x1y0din(x1y0din), .x1y0dout(x1y0dout), .x1y0req_net(x1y0req_net), .x1y0ack_net(x1y0ack_net), .x1y0ack_dp(x1y0ack_dp), .x1y0req_dp(x1y0req_dp), .x1y1din(x1y1din), .x1y1dout(x1y1dout), .x1y1req_net(x1y1req_net), .x1y1ack_net(x1y1ack_net), .x1y1ack_dp(x1y1ack_dp), .x1y1req_dp(x1y1req_dp));
endmodule