代码搜索：sync
找到约 6,244 项符合「sync」的源代码
代码结果 6,244
www.eeworm.com/read/127781/6000241
h ioctl.h
#ifndef __HDLC_IOCTL_H__
#define __HDLC_IOCTL_H__
typedef struct {
unsigned int clock_rate; /* bits per second */
unsigned int clock_type; /* internal, external, TX-internal etc. */
unsigned shor
www.eeworm.com/read/123322/6060443
c io_diag.c
//=============================================================================
//
// io_diag.c
//
// Redirect diag output to the configured console device
//
//=======================================
www.eeworm.com/read/102935/6229792
h ioctl.h
#ifndef __HDLC_IOCTL_H__
#define __HDLC_IOCTL_H__
typedef struct {
unsigned int clock_rate; /* bits per second */
unsigned int clock_type; /* internal, external, TX-internal etc. */
unsigned shor
www.eeworm.com/read/402294/11538868
rc mush.rc
#
# Key bindings similar to those of MUSH
#
# $Id: Mush.rc,v 3.0 2002/01/24 12:11:17 roessler Exp $
bind index . display-message
bind index t display-message
macro index n j\n
bind index + next-entr
www.eeworm.com/read/158164/11639967
vhd tx_inter.vhd
-- ************************************************************************
-- ** REFERENCE DESIGN PART-1 **
-- *******************************************
www.eeworm.com/read/347114/11691186
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_hssi_rx_a1a1a2a2_patdet_sm is
generic(
\SEARCH_A1_1\ : integer := 0;
\SEARCH_A1_2\ : integer := 1;
\SEARCH_A
www.eeworm.com/read/347114/11692899
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_lvds_rx_fifo_sync_ram is
generic(
ram_width : integer := 10
);
port(
clk : in vl_logic;
www.eeworm.com/read/347114/11693448
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_hssi_rx_a1a1a2a2_patdet_sm is
generic(
\SEARCH_A1_1\ : integer := 0;
\SEARCH_A1_2\ : integer := 1;
\SEARCH_A2_1
www.eeworm.com/read/347114/11699381
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_lvds_rx_fifo_sync_ram is
generic(
ram_width : integer := 10
);
port(
clk : in vl_logic;
www.eeworm.com/read/152763/12087064
v firstchannel.v
module firstchannel(
a933_clk ,
a933_rdy,
a933_rvs,
a933_sc,
a933_data_in ,
reset ,
ts_sync ,