代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/326886/13111372
vhd portain.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY portain IS
PORT(
PAIN : IN std_logic_vector (7 DOWNTO 0);
RESET : IN std_logic;
CLK : IN std_logic;
www.eeworm.com/read/326886/13111394
vhd portbin.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY portbin IS
PORT(
PBIN : IN std_logic_vector (7 DOWNTO 0);
RESET : IN std_logic;
CLK : IN std_logic;
www.eeworm.com/read/326886/13111569
vhd portbout.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY portbout IS
PORT(
RESET : IN std_logic;
CLK : IN std_logic;
DIN : IN std_logic_vector (7 DOWNTO 0);
www.eeworm.com/read/241758/13121759
txt ram.txt
CS为RAM的片选信号，WR为RAM的写信号，RD为RAM读信号，ADR：八位地址信号，Din：八位数据输入线，Dout为八位数据输出线。
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM is
port (WR: in STD_LOGIC;
www.eeworm.com/read/326695/13122128
doc vhdlsiweichufaqi.doc
VHDL除法运算
2008-05-22 08:55
引言
???? 在数字计算中，加、减、乘、除运算经常使用。在FPGA中，有加、减、乘、除的算法指令，但除法中除数必须为2的幂，因此无法实现除数为任意数的除法;而二进制除法算法中包含了减法、乘法、数的分解与合成、试商的判断等多种操作过程。因此，除法运算过程非常复杂，用VHDL编写除法运算很难实现。因此，作者根据二进制乘法的原理，采用被除数与除 ...
www.eeworm.com/read/326624/13129113
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/326624/13129153
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/139799/13130372
vhd example12-4.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY latch4 IS
PORT (
clk: IN STD_LOGIC;
reset: IN STD_LOGIC;
data: IN STD_LOGIC;
load: IN std_logic;
q: OUT STD_LOGIC
);
END la
www.eeworm.com/read/139799/13130416
vhd example12-18.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY reg IS
PORT (
data: IN STD_LOGIC_VECTOR (7 downto 0);
clk: IN STD_LOGIC;
enable: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (7 downto 0)
www.eeworm.com/read/139799/13130458
vhd example16-3.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY counter8 IS
PORT (
clk: IN std_logic;
reseta: IN std_logic;
resetb: IN