代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/246102/12756135
vhd pci.vhd
-- megafunction wizard: %PCI Compiler v4.1.1%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- pci_t32
-- ======================
www.eeworm.com/read/144784/12772543
txt 时间扫描模块seltime.vhd.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity seltime is
port(clk1,reset:in std_logic;
sec,min :in std_logic_vector(6
www.eeworm.com/read/144784/12772549
txt 时间扫描模块seltime.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity seltime is
port(clk1,reset:in std_logic;
sec,min :in std_logic_vector(6
www.eeworm.com/read/332117/12777586
vhd compressor_tb.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : JPEG Hardware Compressor Testbench
-- Design : jpeg
-- Author : Vi
www.eeworm.com/read/245646/12785503
vhd portaout.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY portaout IS
PORT(
RESET : IN std_logic;
CLK : IN std_logic;
DIN : IN std_logic_vector (7 DOWNTO 0);
www.eeworm.com/read/245646/12785505
vhd portain.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY portain IS
PORT(
PAIN : IN std_logic_vector (7 DOWNTO 0);
RESET : IN std_logic;
CLK : IN std_logic;
www.eeworm.com/read/245646/12785532
vhd portbin.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY portbin IS
PORT(
PBIN : IN std_logic_vector (7 DOWNTO 0);
RESET : IN std_logic;
CLK : IN std_logic;
www.eeworm.com/read/245646/12785735
vhd portbout.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY portbout IS
PORT(
RESET : IN std_logic;
CLK : IN std_logic;
DIN : IN std_logic_vector (7 DOWNTO 0);
www.eeworm.com/read/331896/12802506
vhd dianti.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dianti is
port ( clk : in std_logic;
www.eeworm.com/read/331763/12809763
vhd sipo.vhd
library ieee;--------8 bits serial input parallel output
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sipo is
port (d_in:in std_logic;