pci.vhd

div的verilog开发程序

-- megafunction wizard: %PCI Compiler v4.1.1%
-- GENERATION: XML

-- ============================================================
-- Megafunction Name(s):
-- 			pci_t32
-- ============================================================
-- Generated by PCI Compiler 4.1.1 [Altera, IP Toolbench v1.2.11 build48]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2007 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

library IEEE;
use IEEE.std_logic_1164.all;

ENTITY pci IS
	PORT (
		clk	: IN STD_LOGIC;
		rstn	: IN STD_LOGIC;
		idsel	: IN STD_LOGIC;
		l_adi	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		lt_rdyn	: IN STD_LOGIC;
		lt_abortn	: IN STD_LOGIC;
		lt_discn	: IN STD_LOGIC;
		lirqn	: IN STD_LOGIC;
		cben	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		framen	: IN STD_LOGIC;
		irdyn	: IN STD_LOGIC;
		intan	: OUT STD_LOGIC;
		serrn	: OUT STD_LOGIC;
		l_adro	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		l_dato	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		l_beno	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		l_cmdo	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		lt_framen	: OUT STD_LOGIC;
		lt_ackn	: OUT STD_LOGIC;
		lt_dxfrn	: OUT STD_LOGIC;
		lt_tsr	: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
		cmd_reg	: OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
		stat_reg	: OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
		perrn	: OUT STD_LOGIC;
		devseln	: OUT STD_LOGIC;
		trdyn	: OUT STD_LOGIC;
		stopn	: OUT STD_LOGIC;
		ad	: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		par	: INOUT STD_LOGIC
	);
END pci;

ARCHITECTURE SYN OF pci IS

attribute altera_attribute : string;

attribute altera_attribute of SYN: ARCHITECTURE is "suppress_da_rule_internal=z100";


	COMPONENT pci_t32
	GENERIC (
		CLASS_CODE	: STD_LOGIC_VECTOR := X"ff0000";
		DEVICE_ID	: STD_LOGIC_VECTOR := X"0004";
		REVISION_ID	: STD_LOGIC_VECTOR := X"01";
		SUBSYSTEM_ID	: STD_LOGIC_VECTOR := X"0000";
		SUBSYSTEM_VENDOR_ID	: STD_LOGIC_VECTOR := X"0000";
		TARGET_DEVICE	: STRING;
		VENDOR_ID	: STD_LOGIC_VECTOR := X"1172";
		MIN_GRANT	: STD_LOGIC_VECTOR := X"00";
		MAX_LATENCY	: STD_LOGIC_VECTOR := X"00";
		CAP_PTR	: STD_LOGIC_VECTOR := X"40";
		CIS_PTR	: STD_LOGIC_VECTOR := X"00000000";
		BAR0	: STD_LOGIC_VECTOR := X"fff00000";
		BAR1	: STD_LOGIC_VECTOR := X"80000000";
		BAR2	: STD_LOGIC_VECTOR := X"fff00000";
		BAR3	: STD_LOGIC_VECTOR := X"fff00000";
		BAR4	: STD_LOGIC_VECTOR := X"fff00000";
		BAR5	: STD_LOGIC_VECTOR := X"fff00000";
		NUMBER_OF_BARS	: STD_LOGIC_VECTOR := X"00000001";
		HARDWIRE_BAR0	: STD_LOGIC_VECTOR := X"00000000";
		HARDWIRE_BAR1	: STD_LOGIC_VECTOR := X"00000000";
		HARDWIRE_BAR2	: STD_LOGIC_VECTOR := X"00000000";
		HARDWIRE_BAR3	: STD_LOGIC_VECTOR := X"00000000";
		HARDWIRE_BAR4	: STD_LOGIC_VECTOR := X"00000000";
		HARDWIRE_BAR5	: STD_LOGIC_VECTOR := X"00000000";
		HARDWIRE_EXP_ROM	: STD_LOGIC_VECTOR := X"00000001";
		EXP_ROM_BAR	: STD_LOGIC_VECTOR := X"fff00000";
		PCI_66MHZ_CAPABLE	: STRING;
		INTERRUPT_PIN_REG	: STD_LOGIC_VECTOR := X"01";
		ENABLE_BITS	: STD_LOGIC_VECTOR := X"00000000"
	);
	PORT (
		clk	: IN STD_LOGIC;
		rstn	: IN STD_LOGIC;
		idsel	: IN STD_LOGIC;
		l_adi	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		lt_rdyn	: IN STD_LOGIC;
		lt_abortn	: IN STD_LOGIC;
		lt_discn	: IN STD_LOGIC;
		lirqn	: IN STD_LOGIC;
		cben	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		framen_in	: IN STD_LOGIC;
		irdyn_in	: IN STD_LOGIC;
		intan	: OUT STD_LOGIC;
		serrn	: OUT STD_LOGIC;
		l_adro	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		l_dato	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		l_beno	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		l_cmdo	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		lt_framen	: OUT STD_LOGIC;
		lt_ackn	: OUT STD_LOGIC;
		lt_dxfrn	: OUT STD_LOGIC;
		lt_tsr	: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
		cmd_reg	: OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
		stat_reg	: OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
		perrn	: OUT STD_LOGIC;
		devseln_out	: OUT STD_LOGIC;
		trdyn_out	: OUT STD_LOGIC;
		stopn_out	: OUT STD_LOGIC;
		ad	: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		par	: INOUT STD_LOGIC
	);

	END COMPONENT;

BEGIN

	pci_t32_inst : pci_t32
	GENERIC MAP (
		CLASS_CODE => X"ff0000",
		DEVICE_ID => X"0004",
		REVISION_ID => X"01",
		SUBSYSTEM_ID => X"0000",
		SUBSYSTEM_VENDOR_ID => X"0000",
		TARGET_DEVICE => "NEW",
		VENDOR_ID => X"1172",
		MIN_GRANT => X"00",
		MAX_LATENCY => X"00",
		CAP_PTR => X"40",
		CIS_PTR => X"00000000",
		BAR0 => X"fff00000",
		BAR1 => X"80000000",
		BAR2 => X"fff00000",
		BAR3 => X"fff00000",
		BAR4 => X"fff00000",
		BAR5 => X"fff00000",
		NUMBER_OF_BARS => X"00000001",
		HARDWIRE_BAR0 => X"00000000",
		HARDWIRE_BAR1 => X"00000000",
		HARDWIRE_BAR2 => X"00000000",
		HARDWIRE_BAR3 => X"00000000",
		HARDWIRE_BAR4 => X"00000000",
		HARDWIRE_BAR5 => X"00000000",
		HARDWIRE_EXP_ROM => X"00000001",
		EXP_ROM_BAR => X"fff00000",
		PCI_66MHZ_CAPABLE => "NO",
		INTERRUPT_PIN_REG => X"01",
		ENABLE_BITS => X"00000000"
	)
	PORT MAP (
		clk  =>  clk,
		rstn  =>  rstn,
		idsel  =>  idsel,
		l_adi  =>  l_adi,
		lt_rdyn  =>  lt_rdyn,
		lt_abortn  =>  lt_abortn,
		lt_discn  =>  lt_discn,
		lirqn  =>  lirqn,
		cben  =>  cben,
		intan  =>  intan,
		serrn  =>  serrn,
		l_adro  =>  l_adro,
		l_dato  =>  l_dato,
		l_beno  =>  l_beno,