portbout.vhd

8255的vhdl 程序

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY portbout IS
   PORT(
      RESET       : IN std_logic;
      CLK         : IN std_logic;
      DIN         : IN std_logic_vector (7 DOWNTO 0);
      PortBOutLd  : IN std_logic;
      PBOUT       : OUT std_logic_vector (7 DOWNTO 0)
   );

END portbout;


ARCHITECTURE rtl OF portbout IS

   SIGNAL    PortBOutRegD : std_logic_vector(7 DOWNTO 0);
   SIGNAL    PortBOutRegQ : std_logic_vector(7 DOWNTO 0);


   BEGIN

	  PBOUT <= PortBOutRegQ;


      PortBOutRegProc: PROCESS ( PortBOutLd, PortBOutRegQ, DIN )

         BEGIN

            IF ( PortBOutLd = '0')  THEN
               PortBOutRegD     <= DIN;
			ELSE
			   PortBOutRegD     <= PortBOutRegQ;
            END IF;

         END PROCESS;


      PortBOutRegSynchProc: PROCESS ( RESET, CLK )

         BEGIN

            IF (RESET = '1') THEN
               PortBOutRegQ     <= "00000000";
            ELSIF ( CLK'EVENT and CLK = '1')  THEN
               PortBOutRegQ     <= PortBOutRegD;
            END IF;

         END PROCESS;

   END rtl;