代码搜索:std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
www.eeworm.com/read/297535/8012263

vhd cnt.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY cnt IS PORT( clk: IN STD_LOGIC; rst: IN STD_LOGIC; adj: IN STD_LOGIC; adjust: IN STD_LOGIC_VECTOR(4 d
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vhd deco10.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY deco10 IS PORT( sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); disable : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END deco10;
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vhd ddr_sdram_debug_design_tb.vhd

-------------------------------------------------------------------------------- -- This confidential and proprietary software may be used only as authorized by -- a licensing agreement from Altera Co
www.eeworm.com/read/297452/8019271

vhd sample.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sample is port(clk : in std_logic; -- load : in std_logic;--实际板子没复位信号 I : in std_logic_vector(13 downto 0)
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vhd regandintmode.vhd

LIBRARY ieee; USE ieee.std_logic_1164.all; -- Entity Declaration ENTITY RegAndIntMode IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( nReset : IN STD_LOGIC; FifoStsRegA
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vhd counter.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter is port( clk: in std_logic; enable: in std_logic; load:
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bak counter.vhd.bak

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter is port( clk: in std_logic; enable: in std_logic; load:
www.eeworm.com/read/297219/8044345

vhd andgate.vhd

------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------------------------------ ENTITY andgate IS PORT( r1,r2,r3: IN STD_LOGIC;
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vhd s3top.vhd

------------------------------------------------------------------------ -- S3demo.vhd -- Demonstrate basic Pegasus function ---------------------------------------------------------------------
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txt 新建 文本文档 (3).txt

--********************************************* -- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; LIBRARY altera; USE altera.