counter.vhd

脉冲发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(
   clk:   in std_logic;
   enable:    in std_logic;
   load:  in std_logic;
   co:  out std_logic;
   data:    in std_logic_vector(7 downto 0);
   q:    buffer std_logic_vector(7 downto 0)
   );
end counter;
architecture counter_behave of counter is
signal pulse:   std_logic;
begin
process(clk,enable)
begin
  if load='1' then
    q<=data;
  else if rising_edge(clk) then
    if enable='1' then
      q<=q-1;
    else
      q<=q;
    end if;
    if q="00000000" then
     q<="00000000";
     pulse<='1';
    else
     pulse<='0';
    end if;
  end if;
  end if;
end process;
co<=pulse;
end counter_behave;