andgate.vhd

脉冲发生器

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
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ENTITY andgate IS
PORT(
     r1,r2,r3:  IN STD_LOGIC;
           t1:  OUT STD_LOGIC);
END andgate;
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ARCHITECTURE andgate_behave OF andgate IS
BEGIN
   PROCESS(r1,r2,r3)
   BEGIN
      t1<=r1 and r2 and r3;
END PROCESS;
END andgate_behave;
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