代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/298792/7935448
vhd swepfre.vhd
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-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
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www.eeworm.com/read/398445/7946179
vhd seltime.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity seltime is
port(ckdsp,reset:in std_logic;
second,minute,hour:in std_logic_vector(7 downto 0);
daout:out std_l
www.eeworm.com/read/398445/7946211
vhd alert.vhd
library ieee;
use ieee.std_logic_1164.all;
entity alert is
port(clkspk:in std_logic;
second,minute:in std_logic_vector(7 downto 0);
speak:out std_logic;
lamp:out std_logic_vector(8 downto 0))
www.eeworm.com/read/198238/7946271
txt 移位寄存器.txt
--
--
---------------------------------------------------------------------------------------
-- DESCRIPTION : Shift register
-- Type : univ
-- Width : 4
--
www.eeworm.com/read/198238/7946402
txt 计数器：generate语句的应用.txt
-- Generated Binary Up Counter
-- The first design entity is a T-type flip-flop.
-- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce
www.eeworm.com/read/198238/7946444
txt 计数器：generate语句的应用.txt
-- Generated Binary Up Counter
-- The first design entity is a T-type flip-flop.
-- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce
www.eeworm.com/read/197597/7984788
txt 计数器：generate语句的应用.txt
-- Generated Binary Up Counter
-- The first design entity is a T-type flip-flop.
-- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce
www.eeworm.com/read/197347/8002862
vhd modelsim testbench vhdl参考模板.vhd
-- VHDL Test Bench Created from source file fifo_new.vhd -- 10:13:22 04/05/2005
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for
www.eeworm.com/read/398133/8004252
vhd freq.vhd
--CNT10.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CNT10 IS
PORT(CLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
ENA:IN STD_LOGIC;
CQ:OUT INTEGER RANGE 0 TO 15;
CARRY_OUT:OU
www.eeworm.com/read/398039/8008821
vhd io_ie.vhd
library ieee;
use ieee.std_logic_1164.all;
entity io_ie is
port(
ED:inout std_logic_vector(15 downto 0);
QED:out std_logic_vector(15 downto 0);
NOE:in std_logic;
CLK:in std_log