freq.vhd

来自「vhdl语言设计频率计」· VHDL 代码 · 共 119 行

--CNT10.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CNT10 IS
PORT(CLK:IN STD_LOGIC;
     CLR:IN STD_LOGIC;
     ENA:IN STD_LOGIC;
     CQ:OUT INTEGER RANGE 0 TO 15;
     CARRY_OUT:OUT STD_LOGIC);
END ENTITY CNT10;
ARCHITECTURE ART OF CNT10 IS
SIGNAL CQI:INTEGER RANGE 0 TO 15;
BEGIN
PROCESS(CLK,CLR,ENA)IS
BEGIN
IF CLR='1'THEN CQI<=0;
ELSIF CLK'EVENT AND CLK='1'THEN
IF ENA='1'THEN
IF CQI<9 THEN CQI<=CQI+1;
ELSE CQI<=0;END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CQI) IS
BEGIN
IF CQI=9 THEN CARRY_OUT<='1';
ELSE CARRY_OUT<='0';END IF;
END PROCESS;
CQ<=CQI;
END ARCHITECTURE ART;
--REG32B.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
PORT(LOAD:IN STD_LOGIC;
     DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
     DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END ENTITY REG32B;
ARCHITECTURE ART OF REG32B IS
BEGIN
PROCESS(LOAD,DIN) IS
BEGIN
IF LOAD'EVENT AND LOAD='1' THEN DOUT<=DIN;
END IF;
END PROCESS;
END ARCHITECTURE ART;
--TESTCTL.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TESTCTL IS
PORT(CLK:IN STD_LOGIC;
     TSTEN:OUT STD_LOGIC;
     CLR_CNT:OUT STD_LOGIC;
     LOAD:OUT STD_LOGIC);
END ENTITY TESTCTL;
ARCHITECTURE ART OF TESTCTL IS
SIGNAL DIV2CLK:STD_LOGIC;
BEGIN
PROCESS(CLK) IS
BEGIN
IF CLK'EVENT AND CLK='1' THEN
DIV2CLK<=NOT DIV2CLK;
END IF;
END PROCESS;
PROCESS(CLK,DIV2CLK) IS
BEGIN
IF CLK='0' AND DIV2CLK='0' THEN
CLR_CNT<='1';
ELSE CLR_CNT<='0';
END IF;
END PROCESS;
LOAD<=NOT DIV2CLK;  TSTEN<=DIV2CLK;
END ARCHITECTURE ART;
--FREQ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FREQ IS
PORT(FSIN:IN STD_LOGIC;
     CLK:IN STD_LOGIC;
     DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END ENTITY FREQ;
ARCHITECTURE ART OF FREQ IS
COMPONENT CNT10 IS
PORT(CLK,CLR,ENA:IN STD_LOGIC;
     CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
     CARRY_OUT:OUT STD_LOGIC);
END COMPONENT CNT10;
COMPONENT REG32B IS
PORT(LOAD:IN STD_LOGIC;
     DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
     DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END COMPONENT REG32B;
COMPONENT TESTCTL IS
PORT(CLK:IN STD_LOGIC;
     TSTEN:OUT STD_LOGIC;
     CLR_CNT:OUT STD_LOGIC;
     LOAD:OUT STD_LOGIC);
END COMPONENT TESTCTL;
SIGNAL SE,SC,SL:STD_LOGIC;
SIGNAL S1,S2,S3,S4,S5,S6,S7,S8:STD_LOGIC;
SIGNAL SD:STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
U0:TESTCTL PORT MAP(CLK=>CLK,TSTEN=>SE,CLR_CNT=>SC,LOAD=>SL);
U1:CNT10 PORT MAP(CLK=>FSIN,CLR=>SC,ENA=>SE,
                  CQ=>SD(3 DOWNTO 0),CARRY_OUT=>S1);
U2:CNT10 PORT MAP(CLK=>S1,CLR=>SC,ENA=>SE,
                  CQ=>SD(7 DOWNTO 4),CARRY_OUT=>S2);
U3:CNT10 PORT MAP(S2,SC,SE,SD(11 DOWNTO 8),S3);
U4:CNT10 PORT MAP(S3,SC,SE,SD(15 DOWNTO 12),S4);
U5:CNT10 PORT MAP(S4,SC,SE,SD(19 DOWNTO 16),S5);
U6:CNT10 PORT MAP(S5,SC,SE,SD(23 DOWNTO 20),S6);
U7:CNT10 PORT MAP(S6,SC,SE,SD(27 DOWNTO 24),S7);
U8:CNT10 PORT MAP(S7,SC,SE,SD(31 DOWNTO 28),S8);
U9:REG32B PORT MAP(LOAD=>SL,DIN=>SD(31 DOWNTO 0),DOUT=>DOUT);
END ARCHITECTURE ART;