swepfre.vhd

这是我的毕业设计

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1i
--  \   \         Application : sch2vhdl
--  /   /         Filename : swepfre.vhf
-- /___/   /\     Timestamp : 10/05/2007 14:43:43
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family virtex4 -flat -suppress -w swepfre.sch swepfre.vhf
--Design Name: swepfre
--Device: virtex4
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity swepfre is
   port ( clk40   : in    std_logic; 
          clk120  : out   std_logic; 
          sin_out : out   std_logic_vector (5 downto 0));
end swepfre;

architecture BEHAVIORAL of swepfre is
   attribute IOSTANDARD  : string ;
   attribute CAPACITANCE : string ;
   attribute BOX_TYPE    : string ;
   signal XLXN_2       : std_logic;
   signal XLXN_3       : std_logic;
   signal XLXN_4       : std_logic;
   signal XLXN_5       : std_logic;
   signal XLXN_7       : std_logic;
   signal XLXN_10      : std_logic_vector (31 downto 0);
   signal XLXN_12      : std_logic_vector (7 downto 0);
   signal clk120_DUMMY : std_logic;
   component IBUFG
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute IOSTANDARD of IBUFG : component is "LVCMOS25";
   attribute CAPACITANCE of IBUFG : component is "DONT_CARE";
   attribute BOX_TYPE of IBUFG : component is "BLACK_BOX";
   
   component dcm_160
      port ( CLKIN_IN   : in    std_logic; 
             RST_IN     : in    std_logic; 
             LOCKED_OUT : out   std_logic; 
             CLKFX_OUT  : out   std_logic; 
             CLK0_OUT   : out   std_logic);
   end component;
   
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : component is "BLACK_BOX";
   
   component rst_gen
      port ( clk : in    std_logic; 
             rst : out   std_logic);
   end component;
   
   component swep_fre
      port ( clk      : in    std_logic; 
             rst      : in    std_logic; 
             accu_out : out   std_logic_vector (31 downto 0));
   end component;
   
   component trunction
      port ( clk           : in    std_logic; 
             phaseaddress  : in    std_logic_vector (31 downto 0); 
             addresscutted : out   std_logic_vector (7 downto 0));
   end component;
   
   component findsin
      port ( clk    : in    std_logic; 
             addr   : in    std_logic_vector (7 downto 0); 
             sinout : out   std_logic_vector (5 downto 0));
   end component;
   
begin
   clk120 <= clk120_DUMMY;
   XLXI_9 : IBUFG
      port map (I=>clk40,
                O=>XLXN_4);
   
   XLXI_10 : dcm_160
      port map (CLKIN_IN=>XLXN_4,
                RST_IN=>XLXN_2,
                CLKFX_OUT=>clk120_DUMMY,
                CLK0_OUT=>open,
                LOCKED_OUT=>XLXN_5);
   
   XLXI_84 : INV
      port map (I=>XLXN_5,
                O=>XLXN_7);
   
   XLXI_85 : rst_gen
      port map (clk=>XLXN_4,
                rst=>XLXN_3);
   
   XLXI_86 : swep_fre
      port map (clk=>clk120_DUMMY,
                rst=>XLXN_7,
                accu_out(31 downto 0)=>XLXN_10(31 downto 0));
   
   XLXI_87 : trunction
      port map (clk=>clk120_DUMMY,
                phaseaddress(31 downto 0)=>XLXN_10(31 downto 0),
                addresscutted(7 downto 0)=>XLXN_12(7 downto 0));
   
   XLXI_90 : findsin
      port map (addr(7 downto 0)=>XLXN_12(7 downto 0),
                clk=>clk120_DUMMY,
                sinout(5 downto 0)=>sin_out(5 downto 0));
   
   XLXI_91 : INV
      port map (I=>XLXN_3,
                O=>XLXN_2);
   
end BEHAVIORAL;