代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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bak vhdl code1.bak

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ffT IS PORT(T,CLK1,RESET:IN BIT; Q,QINV:OUT BIT); END ffT; ARCHITECTURE behav OF ffT IS SIGNAL S:BIT; BEGIN PROCESS BEGIN WAIT UNTIL CLK='1
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bak vhdl code7.bak

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY mux IS port(s:in std_logic_vector(2 downto 0); inp:in std_logic_vector(7 downto 0); op: out std_logic);
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vhd vhdl code7.vhd

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY mux IS port(s:in std_logic_vector(2 downto 0); inp:in std_logic_vector(7 downto 0); op: out std_logic);
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bak vhdl code8.bak

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity counter is port(C, CLR : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter;architecture archi
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vhd vhdl code8.vhd

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity counter is port(C, CLR : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter;architecture archi
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vhd vhdl code5.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ffT IS PORT(T,CLK1,RESET:IN BIT; Q,QINV:OUT BIT); END ffT; ARCHITECTURE behav OF ffT IS SIGNAL S:BIT; BEGIN PROCESS BEGIN WAIT UNTIL CLK='1
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vhd lx8.vhd

library ieee; use ieee.std_logic_1164.all; entity lx8 is port(a :in std_logic_vector(2 downto 0); g1,g2a,g2b :in std_logic; l :out std_logic_vector(7 dow
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vhd vb48.vhd

library ieee; use ieee.std_logic_1164.all; entity vb48 is port(a :in std_logic_vector(3 downto 0); bin :in std_logic; y :out std_logic_vector(
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vhd lx38.vhd

library ieee; use ieee.std_logic_1164.all; entity lx38 is port(a,b,c :in std_logic; g1,g2a,g2b :in std_logic; l :out std_logic_vector(7 downto 0)); end
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c ad0804.c

/////////////////////////// ///A/D转换实验 /////////////////// #include #include //******************************************** //LIBRARY IEEE; //USE IEEE.STD_LOGIC_1164.ALL;
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