代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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vhd multi8x8.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; ENTITY MULTI8X8 IS -- 8位乘法器顶层设计 PORT ( CLKK,START : IN STD_LOGIC; A,
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vhd efepd.vhd

-- Copyright (C) 1991-2007 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o
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vhd dvf.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DVF IS PORT( CLK:IN STD_LOGIC; D :IN STD_LOGIC_VECTOR(7 DOWNTO 0); FOUT:OUT STD_LOGIC); END; A
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txt fenpinqi.txt

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY PULSE8 IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); FOUT
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vhd pulse8.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY PULSE8 IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); FOUT
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vhd andarith.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity andarith is port(abin:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(7 downto 0
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vhd clock.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity clock is port(clk,clk2:in std_logic; show:out std_logic_vector(6 downt
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vhd tran.vhd

Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity tran13to16 is port( a13,b13: in std_logic_vector(12 downto 0); clk:
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vhd register16.vhd

Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity register15 is port( Din: in std_logic_vector(15 downto 0); clk:
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vhd rightshift.vhd

Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity rightshift is port( Din: in std_logic_vector(15 downto 0); clk:
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