代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/363951/9928884
vhd jianfaqi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jianfaqi is
port(A,B:in std_logic_vector(3 downto 0);
s: out std_logic_v
www.eeworm.com/read/168079/9940204
vhd mux21w16.vhd
-- output of CoreGen module generator
-- $Header: mux2VHT.vhd,v 1.2 1998/06/15 17:57:53 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
www.eeworm.com/read/168079/9940219
vhd mux4w16.vhd
-- output of CoreGen module generator
-- $Header: mux4VHT.vhd,v 1.2 1998/06/15 17:58:03 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
www.eeworm.com/read/167830/9951144
vhd keyncode.vhd
LIBRARY IEEE;----库文件
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY keyncode IS----实体
PORT(
key:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q: OUT INTEGER RANGE 0 TO 7;
spken: OUT STD_LOGIC);
www.eeworm.com/read/167697/9955513
txt 计数器：generate语句的应用.txt
-- Generated Binary Up Counter
-- The first design entity is a T-type flip-flop.
-- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce
www.eeworm.com/read/363302/9960714
vhd mux6_1.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mux6_1 is
port(
sel : in std_logic_vector(2 downto 0);
clk : in std_logic;
datain : in std_logic_vector(9 downto 0);
d
www.eeworm.com/read/362976/9972765
vhd shukongdiv.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHUKONG_DIV IS
PORT(CLK:IN STD_LOGIC;
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FOUT:OUT STD_LOGIC);
END SHUKO
www.eeworm.com/read/362976/9972777
vhd notetabs.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY NoteTabs IS
PORT ( clk : IN STD_LOGIC;
CounterOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );
www.eeworm.com/read/167059/9982714
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/362734/9984275
txt ldpc - behavioral.txt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity LDPC is
Port (
clock : in STD_LOGIC;