notetabs.vhd

出血FPGA,用VHDL做的音乐盒

	LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;
	ENTITY NoteTabs IS
	    PORT ( clk    : IN STD_LOGIC;
	        CounterOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );
	END;
	ARCHITECTURE one OF NoteTabs IS
	    SIGNAL Counter :  STD_LOGIC_VECTOR (7 DOWNTO 0);
	BEGIN
	    CNT8 : PROCESS(clk, Counter)
	    BEGIN
	        IF Counter=138 THEN  
				Counter <= "00000000";
	        ELSIF (clk'EVENT AND clk = '1') THEN 
				Counter <= Counter+1; 
			END IF;
	    END PROCESS;
		CounterOUT<=Counter;
	 END one;