代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/169299/9868767
d2_4l
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-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
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www.eeworm.com/read/169299/9868915
vhd dq024.vhd
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-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
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www.eeworm.com/read/365309/9870065
vhd l_conversions_p.vhd
-- Altera Microperipheral Reference Design Version 0802
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-- File Name: l_conversions_p.vhd
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www.eeworm.com/read/365009/9882727
vhd songer.vhd
library ieee;
use ieee.std_logic_1164.all;
entity songer is
port(clk12MHZ:in std_logic;
clk8HZ:in std_logic;
spkout:out std_logic);
end;
architecture one of songer is
component notetabs
por
www.eeworm.com/read/365009/9882731
vhd notetabs.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity notetabs is
port(clk:in std_logic;
toneindex:out std_logic_vector(3 downto 0));
end;
architecture one of note
www.eeworm.com/read/365008/9882876
vhd songer.vhd
library ieee;
use ieee.std_logic_1164.all;
entity songer is
port(clk12MHZ:in std_logic;
clk8HZ:in std_logic;
spkout:out std_logic);
end;
architecture one of songer is
component notetabs
por
www.eeworm.com/read/365008/9882878
vhd notetabs.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity notetabs is
port(clk:in std_logic;
toneindex:out std_logic_vector(3 downto 0));
end;
architecture one of note
www.eeworm.com/read/364988/9884018
vhd sipo.vhd
library ieee;--------8 bits serial input parallel output
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sipo is
port (d_in:in std_logic;
www.eeworm.com/read/364988/9884042
vhd three_spi.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity sig_new is
port(
SCK,SDA,CS : in std_logic;
data : out std_logic_vector(11 downto 0);
www.eeworm.com/read/364651/9899508
vhd i2c_master_top.vhd
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---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level