代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/282462/9092550
vhd second.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;
sec1,sec0:out std_logic_vector(3 downto 0);
co:out std_logic);
www.eeworm.com/read/282462/9092553
vhd minute.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINUTE is
port(clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
e
www.eeworm.com/read/282462/9092571
vhd seltime.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
port(
clk:in std_logic;------扫描时钟
secm1,secm0,sec1,
www.eeworm.com/read/282462/9092580
vhd hour.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;----输入时钟/高电平有效的使能信号
h1,h0:out std_logic_vector(3 downto 0));----时高位/低位
en
www.eeworm.com/read/282462/9092589
vhd second.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;----时钟/清零信号
sec1,sec0:out std_logic_vector(3 downto 0);----秒高位/低位
www.eeworm.com/read/282462/9092593
vhd minute.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINUTE is
port(clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
e
www.eeworm.com/read/381162/9106783
vhd add.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add is
port(clk:in std_logic;
adds:in std_logic_vector(15 downto 0):="0000000000000000";
www.eeworm.com/read/184330/9109155
vhd dcfq.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DCFQ IS
PORT(CLK:IN STD_LOGIC;
D:IN STD_LOGIC;
Q:OUT STD_LO
www.eeworm.com/read/381044/9113121
vhd reg32bit.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg32bit is
port(load:in std_logic;
din:in std_logic_vector(31 downto 0);
dout:out std_logic_vector(31 downto 0));
end reg32bit;
archit
www.eeworm.com/read/381044/9113123
vhd mul16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mul16 is
port (clk:in std_logic;
a,b:in std_logic_vector(15 downto 0);
q:ou