add.vhd

来自「这是一个用vhdl语言实现dds的例子」· VHDL 代码 · 共 22 行

library  ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity add is
   port(clk:in std_logic;
        adds:in std_logic_vector(15 downto 0):="0000000000000000";
        m:in std_logic_vector(7 downto 0);
        back:buffer std_logic_vector(15 downto 0);
        adda:out std_logic_vector(7 downto 0));
end add;

architecture behave of add is
begin 
  process(clk)
    begin
      if(clk'event and clk='1') then
      back<=adds+m;
      adda<=back(15 downto 8);
      end if;
  end process;
end behave;