hour.vhd

整点闹钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;----输入时钟/高电平有效的使能信号
     h1,h0:out std_logic_vector(3 downto 0));----时高位/低位
end HOUR;

architecture hour_arc of HOUR is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);----记数
begin
if clk'event and clk='1' then---上升沿触发
if en='1' then---同时“使能”为1
if cnt1="0010" and cnt0="0011" then
cnt1:="0000";----高位/低位同时为0时
cnt0:="0000";
elsif cnt0<"1001" then----低位小于9时，低位记数累加
cnt0:=cnt0+1;
else
cnt0:="0000";
cnt1:=cnt1+1;-----高位记数累加
end if;
end if;
end if;
h1<=cnt1;
h0<=cnt0;

end process;
end hour_arc;