代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/382070/9051321
vhd a244.vhd
library ieee;
use ieee.std_logic_1164.all;
entity A244 is
port (GN1,GN2 : IN std_logic;
A1,A2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Y1,Y2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END
www.eeworm.com/read/382070/9051326
vhd a138.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY A138 IS
PORT (G1,G2AN,G2BN : IN STD_LOGIC;
A, B, C : IN STD_LOGIC;
YN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END A138
www.eeworm.com/read/282589/9081331
txt aes encryption.txt
--头文件
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilin
www.eeworm.com/read/184671/9086638
vhd serial.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
www.eeworm.com/read/184671/9086654
vhd interface.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
www.eeworm.com/read/184671/9086671
vhd mux.vhd
-------------------------------------------------------------------------------
-- Title : mux
-- Project :
-------------------------------------------------------------------------------
--
www.eeworm.com/read/184671/9086673
vhd conj.vhd
-------------------------------------------------------------------------------
-- Title : Conj.vhd
-- Project :
------------------------------------------------------------------------------
www.eeworm.com/read/184671/9086684
vhd parallel.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
www.eeworm.com/read/282462/9092538
vhd seltime.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
port(
clk:in std_logic;
sec1,sec0,min1,min0,h1,h0:i
www.eeworm.com/read/282462/9092547
vhd hour.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;
h1,h0:out std_logic_vector(3 downto 0));
end HOUR;
architecture hour_