代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/478303/6714452
vhd cordic.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity CORDIC_ELEMENT is
generic(N:integer:=12;--No of bits in register
SHIFT:integer:=0);--Shift count for this stage
p
www.eeworm.com/read/478253/6722747
vhd lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
www.eeworm.com/read/403820/11508967
vhd keydecoder.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY keydecoder_deb IS
PORT(
keyin :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
keydrv :IN STD_LOGIC_VECTOR(3 DOW
www.eeworm.com/read/402018/11543731
vhd butterfly1.vhd
library lpm;
use lpm.lpm_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity butterfly1 is
generic(w2:in
www.eeworm.com/read/402018/11544019
vhd lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
www.eeworm.com/read/155986/11836559
vhd bin_add_4bit.vhd
--************************************
--* 4 Bit Binary Full Adder *
--* Filename : BIN_ADD_4BIT.VHD *
--************************************
library IEEE;
use IEEE.STD_LOGIC_1164
www.eeworm.com/read/339668/12210820
vhd lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
www.eeworm.com/read/234530/14108309
vhd b3x8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity b3x8 is
PORT (CPS : IN STD_LOGIC_VECTOR( 2 DOWNTO 0) ;
YO : OUT STD_L
www.eeworm.com/read/215073/15075604
vhd input_output.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
www.eeworm.com/read/211745/15174359
vhd butterfly1.vhd
library lpm;
use lpm.lpm_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity butterfly1 is
generic(w2:in