代码搜索：std
找到约 10,000 项符合「std」的源代码
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www.eeworm.com/read/414309/11121308
vhd ramdatareg.vhd
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan
www.eeworm.com/read/414309/11121309
vhd avr_uc_comppack.vhd
--************************************************************************************************
-- Component declarations for AVR core
-- Version 2.6A
-- Designed by Ruslan Lepetenok
-- Modif
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vhd ocdprogcp2.vhd
--**********************************************************************************************
-- JTAG "Flash" programmer for AVR Core(cp2 Clock Domain)
-- Version 0.5
-- Modified 20.06.2006
--
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vhd jtagcomppack.vhd
--**********************************************************************************************
-- Components declarations for JTAG OCD and "Flash" Programmer
-- Version 0.2A
-- Modified 31.05.20
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vhd uart_5kvg_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
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vhd uart_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
www.eeworm.com/read/268450/11139298
vhd selec.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY selec IS
PORT( clk: IN STD_LOGIC;
selo: out STD_LOGIC_VECTOR (1 DOWNTO 0));
END selec;
ARCHIT
www.eeworm.com/read/268098/11154449
vhd vga_mem.vhd
-- video memory: each entry in the memory represents a column on the screen => address x coordinate
-- the value of an entry is the y-coordinate on the screen => data y coordinate
library
www.eeworm.com/read/268031/11156138
txt 加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/413190/11163673
vhd cpu.vhd
library ieee;
use ieee.std_logic_1164.all;
entity CPU is
port ( reset, clk: in std_logic;
PortA: inout std_logic_vector(7 downto 0);
PortB: inout std_logic_vector(7 downto 0));
end entity CPU;