代码搜索:std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/294608/8217010
vhd test_vga.vhd
----------------------------------------------------------------------------------
-- This design reads an image from SDRAM and displays it on a VGA monitor
-----------------------------------------
www.eeworm.com/read/193387/8233583
vhd top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port ( sysclk : in std_logic;
reset1 : in std_logic;
www.eeworm.com/read/294351/8238130
vhd xzq.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xzq is
port(s1,s2,s3,s4,s5,s6:in std_logic_vector(3 downto 0);
e60,e20,e5:in std_logic;
d1,d0:out std
www.eeworm.com/read/393841/8260216
vhd command.vhd
--
-- LOGIC CORE: Command module
-- MODULE NAME: command()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- REVISION HIST
www.eeworm.com/read/393840/8260450
vhd ddr_command.vhd
--
-- LOGIC CORE: DDR Command module
-- MODULE NAME: ddr_command()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- REVIS
www.eeworm.com/read/393840/8260481
vhd ddr_command.vhd
--
-- LOGIC CORE: DDR Command module
-- MODULE NAME: ddr_command()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- REVIS
www.eeworm.com/read/293226/8305768
vhd xspcore.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
www.eeworm.com/read/293226/8305781
vhd xspuc.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
www.eeworm.com/read/293226/8305797
vhd xspusb.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
www.eeworm.com/read/392763/8327436
vhd clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port( okk,clkk,clrr : in std_logic;
enen: in std_logic;
aa,bb: in std_logic_vector(2 downt