clock.vhd

4位二进制密码锁,可能会对别人有点帮助,大家下来看看把

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port( okk,clkk,clrr : in std_logic;
      enen: in std_logic;
      aa,bb: in std_logic_vector(2 downto 0);
      mm,nn: out std_logic_vector(2 downto 0);
      qq,oo,pp: out std_logic);
end;
architecture behave of clock is
component input
port(en: in std_logic;
     a,b: in std_logic_vector(2 downto 0);
     m1,n1: out std_logic_vector(2 downto 0);
      c: out std_logic_vector(5 downto 0));
end component;
component compare
port(clk,ok : in std_logic;--计时时钟
     d,e : in std_logic_vector(5 downto 0);
     f: out std_logic_vector(5 downto 0);
     g: out std_logic);
end component;   
component flip
port(clk : in std_logic;--计时时钟
     clr : in std_logic;--复位
     h:in std_logic_vector(5 downto 0);
     m: out std_logic_vector(5 downto 0)); 
end component;   
component output
port (n: in std_logic;
      o,p,q: out std_logic);
end component;   
signal cd,fh,me: std_logic_vector(5 downto 0);
signal gn: std_logic;
begin
u1: input port map ( en => enen,a=>aa,b=>bb,c=>cd,m1=>mm,n1=>nn);
u2: compare port map ( ok=>okk,clk=>clkk,d=>cd,e=>me,g=>gn,f=>fh);
u3: flip port map   ( clr=>clrr,clk=>clkk,h=>fh,m=>me);
u4: output port map (n=>gn,o=>oo,p=>pp,q=>qq);
end behave;