xzq.vhd

交通灯VHDL设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xzq is
port(s1,s2,s3,s4,s5,s6:in std_logic_vector(3 downto 0);
     e60,e20,e5:in std_logic;
     d1,d0:out std_logic_vector(3 downto 0));
end xzq;
architecture rr of xzq is
begin
process(e5,e20,e60)
begin
if e60='0' then
  d0<=s1;
  d1<=s2;
elsif e20='0' then
  d0<=s3;
  d1<=s4;
elsif e5='0' then
  d0<=s5;
  d1<=s6;
end if;
end process;
end rr;