代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/149929/12330577
vhd dataclk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--****************************
entity dataclk is
port(
clk:in std_logic;
reset:i
www.eeworm.com/read/149929/12331323
vhd ex88.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ex88 IS
PORT
(
in1,in2 : STD_LOGIC_vector;
pout : OUT STD_LOGIC_vector
);
END ex88;
ARCHITECTURE a OF ex88 IS
BEGIN
PR
www.eeworm.com/read/149929/12331857
vhd dataclk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--****************************
entity dataclk is
port(
clk:in std_logic;
reset:i
www.eeworm.com/read/149929/12333075
vhd dataclk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--****************************
entity dataclk is
port(
clk:in std_logic;
reset:i
www.eeworm.com/read/149674/12358205
txt 0.txt
测试向量（Test Bench）和波形产生：VHDL实例---加法器源程序新手入门
PLD概述/原理
发展历程
FPGA原理
HDL 概述
学习资料
www.eeworm.com/read/149607/12362912
vhd testadder.vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/149607/12362915
vhd adder.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
www.eeworm.com/read/149607/12363012
txt adder_variety_style.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/250454/12405564
vhd dff89.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff89 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTO
www.eeworm.com/read/250454/12405588
vhd dff15.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff15 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Dout : OUT STD_LOGIC_VECT