dataclk.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--****************************
entity dataclk is
port(
   clk:in std_logic;
   reset:in std_logic;
   chem,cheh:in std_logic;
   a,b,c:in std_logic;
   q:in std_logic_vector(6 downto 0)
   );
end dataclk;
--*****************************
architecture struct of dataclk is
component counter60s 
port(
    clk:in std_logic;
    resets:in std_logic;
    rcos:out std_logic;
   qh,ql:buffer std_logic_vector(3 downto 0)
   );
end component;
component counter60m 
port(
    rcos:in std_logic;
    resetm:in std_logic; 
    chem:in std_logic;
    rcom:out std_logic;
     qh,ql:buffer std_logic_vector(3 downto 0)
   );
end component;
component counter24 
port(
    rcom:in std_logic;
    reseth:in std_logic;
    cheh:in std_logic;
    qh,ql:buffer std_logic_vector(3 downto 0)
    );
end component;
component ss 
port(
   a,b,c:in std_logic;
   x1:in std_logic_vector(3 downto 0);
   x2:in std_logic_vector(3 downto 0);
   x3:in std_logic_vector(3 downto 0);
   x4:in std_logic_vector(3 downto 0);
   x5:in std_logic_vector(3 downto 0);
   x6:in std_logic_vector(3 downto 0);
   y:out std_logic_vector(3 downto 0)
   );
end component;
component text47 
port(
    num:in std_logic_vector(3 downto 0);
    q:out std_logic_vector(6 downto 0)
    );
end component;
signal s1,s2:std_logic;
signal qls_tmp,qhs_tmp:std_logic_vector(3 downto 0);
signal qlm_tmp,qhm_tmp:std_logic_vector(3 downto 0);
signal qlh_tmp,qhh_tmp:std_logic_vector(3 downto 0);
signal y1:std_logic_vector(3 downto 0);
begin
process(clk,reset,s1,s2,qhs_tmp,qls_tmp,qhm_tmp,qlm_tmp,qhh_tmp,qlh_tmp,chem,cheh,a,b,c)
begin
u1:counter60s port map(clk,reset,s1,qhs_tmp,qls_tmp);
u2:counter60m port map(s1,reset,chem,s2,qhm_tmp,qlm_tmp);
u3:counter24 port map(s2,reset,cheh,qhh_tmp,qlh_tmp);
u4:ss port map(a,b,c,qls_tmp,qhs_tmp,qlm_tmp,qhm_tmp,qlh_tmp,qhh_tmp,y1);
u5:text47 port map(y1,q);
end process;
end struct;