代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/263999/11333293
vhd ad.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ad is
port
(clk:in std_logic;
reset:in std_logic;
ad_int:in std_logic;
da
www.eeworm.com/read/408878/11366526
vhd count10.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT10 IS
PORT(CLK:IN STD_LOGIC; ----时钟信号
Y0:OUT STD
www.eeworm.com/read/263314/11367778
vhd testadder.vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/263314/11367780
vhd adder.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
www.eeworm.com/read/263314/11367851
txt adder_variety_style.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/263013/11380394
vhd clock.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clock IS
PORT (set,date,clo,clk,rst : IN STD_LOGIC;
co1,co2,co3,co4,co5,co6 : OUT STD_LOGIC_VECTO
www.eeworm.com/read/408535/11383428
vhd top_tb.vhd
-- testbench for VHDL
library IEEE;
library work;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity testbench is
-- port (data : inout std_logic_vecto
www.eeworm.com/read/407964/11406973
vhd shift16.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
arch
www.eeworm.com/read/407963/11406975
vhd bidircnt.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic
www.eeworm.com/read/407961/11406999
vhd cntlden.vhd
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;