top_tb.vhd

modelsim仿真流程

-- testbench for VHDL
library IEEE;
library work;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity testbench is
--	port (data : inout std_logic_vector(7 downto 0));	-- ouput port
end entity testbench;

architecture test_top of testbench is

	component top is
		port ( clk,rst : in std_logic;
		-- CPU interface
		addr : in std_logic_vector(11 downto 1);
		data : inout std_logic_vector(7 downto 0);
		ion : inout std_logic_vector(5 downto 0);
		ncs,nwe,noe : in std_logic;
		-- LPT interface
		wpd : out std_logic_vector(7 downto 0);
		nerr,nack,wbusy,wpe : in std_logic;
		wstb : out std_logic;
		-- FPGA configure interface
		dclk,data0,ncfg : out std_logic;
		nstatus,cfg_done : in std_logic;
		-- password interface
		pwd_do : out std_logic;
		pwd_clk,pwd_di,pwd_rst : in std_logic);
	end component;
	
--	component top.shift is
--		port ( clk,rst : in std_logic);
--	end component;

	signal clk,rst : std_logic;
	-- CPU interface
	signal addr : std_logic_vector(11 downto 1);
	signal data : std_logic_vector(7 downto 0);
	signal ion : std_logic_vector(5 downto 0);
	signal ncs,nwe,noe : std_logic;
	-- LPT interface
	signal wpd : std_logic_vector(7 downto 0);
	signal nerr,nack,wbusy,wpe : std_logic;
	signal wstb : std_logic;
	-- FPGA configure interface
	signal dclk,data0,ncfg :  std_logic;
	signal nstatus,cfg_done : std_logic;
	-- password interface
	signal pwd_do : std_logic;
	signal pwd_clk,pwd_di,pwd_rst : std_logic;
	signal count : std_logic_vector(11 downto 1);
	
	constant ClockPeriod : TIME := 50 ns;
	
	begin
	dut : top port map
	      (clk => clk, rst => rst,
			addr => addr, data => data, ion => ion,
			ncs => ncs, nwe => nwe, noe => noe,
			wpd => wpd, nerr => nerr, nack => nack,
			wbusy => wbusy, wpe => wpe, wstb => wstb,
			dclk => dclk, data0 => data0, ncfg => ncfg,
			nstatus => nstatus, cfg_done => cfg_done, 
			pwd_do => pwd_do, pwd_clk => pwd_clk, pwd_di => pwd_di, pwd_rst => pwd_rst
			);
				
	
	--work.shift(rst => rst,clk => clk);
	clock : process 
	begin	-- generate clock
		-- clk <= not clk after (ClockPeriod / 2);
		clk <= '0';
		loop
		   wait for 10ns; 
		   clk <= not clk;
		end loop;
	end process clock;
   
   cnt : process(rst,clk)
	begin 
	    if rst = '0' then
	        count <= (others => '0');
	    elsif rising_edge(clk) then
	        count <= count + 1;
	    end if;
	end process;
	
	run_sim : process 
	begin
		rst <= '0';
		data <= (others => 'Z');
		addr <= (others => '0');
		wpd <= (others => '0');
		ncs <= '1';
		nwe <= '1';
		noe <= '1';
		dclk <= '0';
		data0 <= '0';
		wait for 10ns;
		rst <= '1';
		wait for 50 ns;
		ncs <= '0';
		wait for 20ns;
		addr <= "00000000001";
		data <= "00001011";
		wait for 20ns;
		nwe <= '0';
		wait for 50ns;
		nwe <= '1';
		wait for 40ns;
		ncs <= '1';
		
		wait for 100 ns;
		ncs <= '0';
		wait for 20ns;
		addr <= "00000000000";
		data <= "01001011";
		wait for 20ns;
		nwe <= '0';
		wait for 50ns;
		nwe <= '1';
		wait for 40ns;
		ncs <= '1';
		wait for 5*1000 ns;
		
	--	wait; -- forever
	end process;

end architecture test_top;