代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/476862/6752311
cmp ncofsymbol.cmp
-- Generated by NCO 7.2 [Altera, IP Toolbench 1.3.0 Build 203]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ********
www.eeworm.com/read/410844/11267471
vhd dsp_port80m.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : dsp_port
-- Design : RC_CKJH
-- Author : 杨云龙
-- Company : 北京百
www.eeworm.com/read/410839/11267518
vhd div5.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
www.eeworm.com/read/410825/11267792
vhd dsp_port.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : dsp_port
-- Design : RC_CKJH
-- Author : 杨云龙
-- Company : 北京百
www.eeworm.com/read/410626/11274392
bak eda.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY EDA IS
PORT( funset:in std_logic;
fqset,clk:in std_logic;
update:out std_logic_vector(7 downto 0));
END ENTITY EDA;
ARCH
www.eeworm.com/read/410626/11274394
vhd eda.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY EDA IS
PORT( funset:in std_logic;
fqset,clk:in std_logic;
update:out std_logic_vector(7 downto 0));
END ENTITY EDA;
ARCH
www.eeworm.com/read/264936/11293594
vhd clock.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clock IS
PORT (set,date,clo,clk,rst : IN STD_LOGIC;
co1,co2,co3,co4,co5,co6 : OUT STD_LOGIC_VECTO
www.eeworm.com/read/264932/11294038
vhd finish.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
-----------------------------------------------------
www.eeworm.com/read/264932/11294093
vhf finish.vhf
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
-----------------------------------------------------
www.eeworm.com/read/264187/11326610
vhd chk1101.vhd
library ieee;
use ieee.std_logic_1164.all;
entity chk1101 is
port(din: in std_logic_vector(3 downto 0);
clk: in std_logic;
en: in std_logic;
--clr: in std_logic;