chk1101.vhd

序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器

library ieee;
use ieee.std_logic_1164.all;
entity chk1101 is
  port(din: in std_logic_vector(3 downto 0);
       clk: in std_logic;
        en: in std_logic;
       --clr: in std_logic;
         --d: in std_logic_vector(20 downto 0);
         r: out std_logic);
end chk1101;
architecture rtl of chk1101 is
   --signal reg:std_logic_vector(20 downto 0);
     signal d: std_logic_vector(20 downto 0);
     signal F: std_logic;
begin
  process(clk)--clr)
  begin
      if(en='1')then
    d<="101110101101101001011";
   --if(clr='1')then  
       --reg<='000000000000000000000'
     elsif(clk'event and clk='1')then
       if(d(20 downto 17)=din)then
           F<='1';
       elsif(d(16 downto 13)=din)then
           F<='1';
       elsif(d(12 downto 9)=din)then
           F<='1';
       elsif(d(8 downto 5)=din)then
           F<='1';
       elsif(d(4 downto 1)=din)then
           F<='1';
       else
           F<='0';
       r<=F;
     end if;
   end if;
  end process;
end rtl;