dsp_port80m.vhd

响铃和内存管理功能的VHDL语言

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--
-- Title       : dsp_port
-- Design      : RC_CKJH
-- Author      : 杨云龙
-- Company     : 北京百科融创科技有限公司
--
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--
-- File        : dsp_port.vhd
-- Generated   : Tue Nov 24 10:28:46 2003
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {lcd_port} architecture {a}}

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;


entity DSP_PORT is
Port (   D_IN : inout std_logic_vector(15 downto 0);--DSP DATA_BUS
    A : in std_logic_vector(22 downto 0);   --DSP ADDRESS_BUS
    XF : in std_logic;              --DSP EXT.FLAG
    IOSTRB : in std_logic;
    MSTRB : in std_logic;
    DSP_RW : in std_logic;
    DSPIS : in std_logic;
    DS : in std_logic;
    PS : in std_logic;
    DSP_CLKOUT_IN : in std_logic;     --100MHz
--    DSP_TOUT : in std_logic;
--    DSP_BCLKER : out std_logic;
--    DSP_BFSR0 : out std_logic;
--    DSP_BCLKX : in std_logic;
--    DSP_BFSX0 : in std_logic;
    SRAM_CE : out std_logic;
    SRAM_OE : out std_logic;
    SRAM_WE : out std_logic;
    FLASH_CE : out std_logic;
    FLASH_OE : out std_logic;
    FLASH_WE : out std_logic;
    FLASH_WE_EN :  in std_logic;
--    IC2_OE : out std_logic;
    IC2_TR : out std_logic;
--    IC1_TR : out std_logic;
--    IC1_OE : out std_logic;
--    IC3_OE : out std_logic;
--    IC3_TR : out std_logic;
    --LCD BUS 
    LCD_D : inout std_logic_vector(7 downto 0);
    LCD_RD : out std_logic;
    LCD_WR : out std_logic;
    LCD_CD : out std_logic;
    LCD_CE : out std_logic;
    LCD_FS : out std_logic;
    U38_OE1 : out std_logic;
    U38_OE2 : out std_logic;
    U38_TR1 : out std_logic;
    U38_TR2 : out std_logic;
    LCD_RST: out  std_logic;

    --AD AND DA SAMPLE CLOCK
    CLK_AD : out std_logic;
    --AD1
    AD1_OUT : in std_logic;
    AD1_CS : out std_logic;
    --AD2
    AD2_OUT : in std_logic;
    AD2_CS : out std_logic;
    --AD3   
    AD3_OUT : in std_logic;
    AD3_CS : out std_logic;
    --AD4
    AD4_OUT : in std_logic;
    AD4_CS : out std_logic;     
    --AD5
    AD5_OUT : in std_logic;
    AD5_CS : out std_logic;
    
    --DA
    DA_DIN : OUT std_logic_vector(1 downto 0);
    DA_CS : out std_logic_vector( 1 downto 0);
    DA_CLK : out std_logic_vector( 1 downto 0);

    --USEER 1 CONTROL
    M1_SHK : in std_logic;
    --USEER 2 CONTROL
    M2_SHK : in std_logic;
    --USEER 3 CONTROL
    M3_SHK : in std_logic;
    --USEER 4 CONTROL
    M4_SHK : in std_logic;

    --USER RING CONTROL
    USER_RC : out std_logic_vector(3 downto 0);

    --EXT.LINE CONTROL
    RING_D : in std_logic;        --EXT.LINE RINGING DETECTED
    PASSC : out std_logic;        --EXT.LINE SWITCH ON CONTROL  

    --PCM INTERFACE
    PCM_AT: in std_logic;
    PCM_BT: in std_logic;
    PCM_CT: in std_logic;
    PCM_DT: in std_logic;
    PCM_ET : in std_logic;
    PCM_AR : out std_logic;
    PCM_BR : out std_logic;
    PCM_CR : out std_logic;
    PCM_DR : out std_logic;
    PCM_ER : out std_logic;
    FS_AR : out std_logic;
    FS_BR : out std_logic;
    FS_CR : out std_logic;
    FS_DR : out std_logic;
    FS_ER : out std_logic;
    FS_AT : out std_logic;
    FS_BT : out std_logic;
    FS_CT : out std_logic;
    FS_DT : out std_logic;
    FS_ET : out std_logic;
    PCM_BS : out std_logic;
    --RELAY PORT
    TR_PCMX : out std_logic; 
    TR_FX : out std_logic;
    TR_BX : out std_logic;
--    TR_PCMR : in std_logic;
--    TR_FR : in std_logic;
--    TR_BR : in std_logic;

    --EXT_RAM
    EXT_RAM_D : inout std_logic_vector(7 downto 0);
    EXT_RAM_A : out  std_logic_vector(14 downto 0);
    EXT_RAM_OE : out  std_logic;
    EXT_RAM_CE : out  std_logic;
    EXT_RAM_WR : out  std_logic;

    --KEY BOARD
    KEY : in std_logic_vector(5 downto 0);

    --clock
    SYS_CLK_IN : in std_logic;--16.384MHz

    --reset   
    RST_IN: in std_logic;

    --uart port
    connect_pc : out std_logic;
    txd : out std_logic;
    rxd : in std_logic;
    uart_int:out std_logic;
    --test
--    TEST : out std_logic_vector(4 downto 0);
    dsp_clk_divout : out std_logic  
--    key_cs_out,bus_ctl_out: out std_logic
    );
end DSP_PORT;

architecture a of DSP_PORT is
--component DECLARATION

component IBUFG
      port (I : in STD_LOGIC; O : out std_logic);
end component;

component IBUF
      port (I : in STD_LOGIC; O : out std_logic);
end component;

component div_clk
  PORT(
    CLK, CLR: IN  STD_LOGIC;
    Q5 : OUT  STD_LOGIC);
end component;

component mem_control
  port (
  MSTRB : in std_logic;
  A19 : in std_logic;
  PS : in std_logic;
  RW : in std_logic;
  DS : in std_logic;
  XF : in std_logic;
  SRAM_CE : out std_logic;
  SRAM_WE : out std_logic;
  SRAM_OE : out std_logic;
  FLASH_CE : out std_logic;
  FLASH_WE : out std_logic;
  FLASH_OE : out std_logic
  );
 end component ;

component system_io
  port (
  DSPIS : in std_logic;
  RW : in std_logic;
  A: in std_logic_vector(19 downto 0);
  FLAG_BLOCK_DATA : in std_logic_vector( 15 downto 0);  -- ,FFA_D_TMP
  SYSTEM_FLAG2_DATA : in std_logic_vector(15 downto 0);
  AD1_DATA : in std_logic_vector( 7 downto 0);
  AD2_DATA : in std_logic_vector( 7 downto 0);
  AD3_DATA : in std_logic_vector( 7 downto 0);
  AD4_DATA : in std_logic_vector( 7 downto 0);
  AD5_DATA : in std_logic_vector( 7 downto 0); 
  KEY_DATA : in std_logic_vector( 5 downto 0);
  DSP_DATA_OUT : out std_logic_vector( 15 downto 0);
  DA_DATA_TEMP : out std_logic_vector( 15 downto 0);
  KEY_CS : out std_logic;
  IC2_TR : out std_logic;
  LCD_RAM_CS : out std_logic; 
  AD_FIFO_RDCS : out std_logic_vector(4 downto 0);
  DA_BLOCK_CS : out std_logic_vector(3 downto 0);
  PCM_USER_INFO_CS : out std_logic;  
  EXCHANGE_MOD_CS : out std_logic;
  USER_RING_CONTROL_CS : out std_logic ;
--uart
  uart_data_out : in std_logic_vector(7 downto 0);
   uart_tx_fifo_wrcs : out std_logic;
   uart_rx_fifo_rdcs : out std_logic

  );
end component ;

component system_flag
  port(
  LCD_RAM_FLAG: in std_logic;
  EXT_RING_STA: in std_logic;
  SHK_TMP: in std_logic_vector(3 downto 0);
  DA_FLAG: in std_logic_vector( 3 downto 0);
  AD_FLAG: in std_logic_vector(4 downto 0);
  KEY_FLAG: in std_logic;
  DSP_CLK : in std_logic;
  CLR : in std_logic; 
--  PCM_CS: in std_logic; 
  KEY_CS : in std_logic;
--  AD_FIFO_RDCS : in std_logic_vector(4 downto 0);
--  PCM_FLAG_CLR : out std_logic;
  KEY_FLAG_CLR : out std_logic;
--  AD_FLAG_CLR : out std_logic_vector(4 downto 0); 
  FLAG_BLOCK_DATA : out std_logic_vector(15 downto 0)
  );
end component ;

component system_flag2
  port(
  sta1: in std_logic;
  sta2: in std_logic;
  SYSTEM_FLAG2_DATA : out std_logic_vector(15 downto 0)
  );
end component ;
component user_sta
  port(
  CLK_256K ,CLR: in std_logic;
--  CLR : in std_logic;
  M1_SHK,M2_SHK,M3_SHK,M4_SHK: in std_logic;  -- ,RING_D 
  SHK_TMP : out std_logic_vector(3 downto 0)
--  EXT_RING_STA : out std_logic
  );
end component;
component user_ring
  port (
  CLR : in std_logic;
  RW : in std_logic;
  USER_RING_CONTROL_CS : in std_logic;
  DSP_DATA_IN : in std_logic_vector(15 downto 0); 
  USER_RC  : out std_logic_vector( 3 downto 0);
  PASSC : out std_logic
  );
end component ;
component key_control
  port(
    KEY : in std_logic_vector(5 downto 0);
    SCAN_CLK : in std_logic;
    KEY_FLAG_CLR ,CLR: in std_logic;
    KEY_FLAG : out std_logic;
    KEY_DATA : out std_logic_vector(5 downto 0)
  );
end component;
  
component lcd_port
port(  
    LCD_CLK : in std_logic;  --CLK_1024K
    DSP_CLK : in std_logic; --100MHz
    CLR : in std_logic;
    DSP_RW : in std_logic;
    LCD_RAM_CS : in std_logic;
    BUS_CTL_OUT: out std_logic;
    EXT_RAM_WE_O : out STD_LOGIC;
    EXT_RAM_OE_O : out STD_LOGIC;
    EXT_RAM_CE_O : out STD_LOGIC; 
    EXT_RAM_A_O : out STD_LOGIC_VECTOR(11 downto 0) ;
    EXT_RAM_D_IN : in STD_LOGIC_VECTOR(7 downto 0) ;
    LCD_RAM_RD_OVER : out std_logic;
    DSP_ADDRESS : in std_logic_vector( 11 downto 0);
    LCD_DIN :  in std_logic_vector( 7 downto 0);
    LCD_DOUT : out std_logic_vector( 7 downto 0);
    LCD_RD_O : out std_logic;
    LCD_WR_O : out std_logic;
    LCD_CE_O : out std_logic;  
    LCD_CD_O : out std_logic
    --    LCD_RST_O : out std_logic
    );
end component;


component ext_ring_dete
  port (
  CLK : in std_logic;
  PASSC_TMP : in std_logic;
  EXT_STA:  out std_logic;
  CLR : in std_logic;
  RING_D : in std_logic;
  EXT_RING_DETECTED : out std_logic
  );
end component ;

component pcm_exchange
  port (
    DSP_DATA_IN :in std_logic_vector(15 downto 0);
    SYS_CLK : in std_logic;    
    RW: in std_logic; 
    CLK_100M : in std_logic;  --100M : dsp clk out
    CLR: in std_logic;
    EXCHANGE_MOD_CS: in std_logic;
    PCM_USER_INFO_CS : in std_logic;
    PCM_AT : in std_logic;
    PCM_BT : in std_logic;
    PCM_CT : in std_logic;
    PCM_DT : in std_logic;
    PCM_ET : in std_logic;
    PCM_AR : out std_logic;
    PCM_BR : out std_logic;
    PCM_CR : out std_logic;
    PCM_DR : out std_logic;
    PCM_ER : out std_logic;  
    FS_AR : out std_logic;  
    FS_BR : out std_logic;  
    FS_CR : out std_logic;  
    FS_DR : out std_logic;  
    FS_ER : out std_logic;       
    FS_AT : out std_logic;  
    FS_BT : out std_logic;  
    FS_CT : out std_logic;  
    FS_DT : out std_logic;  
    FS_ET: out std_logic;       
    PCM_BS : out std_logic;
    CLK_8192K_OUT :out std_logic;
    CLK_4096K_OUT :out std_logic;
    CLK_2048K_OUT :out std_logic;
    CLK_1024K_OUT :out std_logic;
    CLK_512K_OUT :out std_logic;
    CLK_256K_OUT:out std_logic;
    CLK_128K_OUT:out std_logic;
    CLK_64K_OUT :out std_logic
--    RELAY: out std_logic_vector(3 downto 0)
  );
end component ;



--SIGNAL
signal RW: std_logic;
signal RST : std_logic;
signal DSP_DATA_IN : std_logic_vector(15 downto 0);      --data bus temp  ,FFA_D_TMP
signal DSP_DATA_OUT : std_logic_vector(15 downto 0);      --data bus temp
--key block signal
signal KEY_CS : std_logic;--KEY BOARD CE AND OE
signal KEY_DATA: std_logic_vector(5 downto 0);  --key board data bus
--PCM CHANGER BLOCK CONTROL SIGNAL
--signal PCM_DATA : std_logic_vector(15 downto 0);  --PCM CONTROL DATA BUS
--signal PCM_RW : std_logic;-- PCM BLOCK RW IN
signal PCM_CS : std_logic;-- PCM BLOKC CS IN
-- AD SIGNAL
signal AD_FIFO_RDCS: std_logic_vector(4 downto 0);
signal AD1_DATA,AD2_DATA,AD3_DATA,AD4_DATA,AD5_DATA : std_logic_vector(7 DOWNTO 0);
signal START_AD1,START_AD2,START_AD3,START_AD4,START_AD5 : std_logic;
--DA SIGNAL
signal DA_FLAG,DA_BLOCK_CS : std_logic_vector( 3 downto 0);
signal DA_DATA_TEMP : std_logic_vector( 15 downto 0);
--LCD BLOCK SIGNAL
signal LCD_DIN,LCD_DOUT :  std_logic_vector(7 downto 0);
signal LCD_RD_TEMP :  std_logic;
signal LCD_WR_TEMP :  std_logic;
signal LCD_CD_TEMP :  std_logic;
signal LCD_CE_TEMP :  std_logic;
signal LCD_FS_TEMP :  std_logic; 
--signal LCD_RST_TEMP : std_logic;   
signal LCD_RAM_CS : std_logic;

signal LCD_RAM_RD_OVER ,EXT_RAM_WR_TMP ,EXT_RAM_OE_TMP ,EXT_RAM_CE_TMP: std_logic;
signal EXT_RAM_D_IN,EXT_RAM_D_OUT : std_logic_vector(7 downto 0);


--signal LCD_DATA : std_logic_vector(7 downto 0);
--FLAG BLOCK SIGNAL
signal FLAG_BLOCK_DATA: std_logic_vector(15 DOWNTO 0);
--ECHO EXT.BLOCK'S FLAG SIGNAL
signal KEY_FLAG,KEY_FLAG_CLR,PCM_FLAG,PCM_FLAG_CLR : std_logic;
signal AD_FLAG : std_logic_vector(4 downto 0);--  ,AD_FLAG_CLR

--SYSTEM CLOCK GEneric BLOCK
signal CLK_8192K : std_logic;
signal CLK_4096K : std_logic;
signal CLK_2048K : std_logic;
signal CLK_1024K : std_logic;
signal CLK_512K : std_logic;
signal CLK_256K: std_logic;
signal CLK_128K: std_logic;
signal CLK_64K : std_logic;
signal CLK_20000K : std_logic;--16M
signal CLK_10000K : std_logic;--8M
signal CLK_4000K : std_logic; --3.2M
signal CLK_2000K : std_logic; --1.6M
signal CLK_1000K : std_logic; --800K
signal CLK_640K: std_logic;--640k
signal CLK_500K : std_logic;  --400K
signal CLK_250K : std_logic;  --200K
signal CLK_160K: std_logic;   --160K

--PCM_BLOCK
--signal FS_AT ,FS_BT,FS_CT ,FS_DT ,FS_ET : std_logic;
signal PCM_USER_INFO_CS :std_logic;
--signal RELAY :std_logic_vector(3 downto 0);
--signal EN_T_MODEL,EN_S_MODEL : std_logic;
signal EXCHANGE_MOD_CS: std_logic;
signal SHK_TMP : std_logic_vector(3 downto 0);
--signal PCM_FS : std_logic_vector(31 downto 0);
--signal EXT_RING_STA : std_logic;
signal PASSC_TMP : std_logic;
signal USER_RING_CONTROL_CS : std_logic;
signal EXT_RING_DETECTED ,EXT_STA_TMP: std_logic;
signal CLR : std_logic;
--signal flag_out : std_logic_vector(1 downto 0);
signal SYS_CLK,DSP_CLKOUT : std_logic;
--uart block signal
signal uart_data_in, uart_data_out : std_logic_vector( 7 downto 0);
signal uart_tx_fifo_wrcs, uart_rx_fifo_rdcs : std_logic;
signal SYSTEM_FLAG2_DATA : std_logic_vector(15 downto 0);
signal uart_tx_busy : std_logic;
signal connect_pc_tmp : std_logic;

--SIGNAL TEST_TMP : STD_LOGIC_VECTOR( 7 DOWNTO 0);

begin

-- Bi-Directional Output Assignments
--DSP,RAM,FLASH control signal connection
DATA_BUS_CONNECTION: block 
signal FLASH_WE_TMP : std_logic;
begin
--  D_IN <= (others=>'Z') WHEN (DSPIS='1'  OR RW='0')
--                    ELSE  DSP_DATA_OUT;
  --DSP_DATA_IN <= DSP_DATA_IN WHEN (DSPIS='1'  OR RW='1')
   --                 ELSE  D_IN;
  D_IN <= DSP_DATA_OUT WHEN (IOSTRB ='0' AND RW ='1' AND DSPIS ='0') ELSE (others=>'Z');
  DSP_DATA_IN <= D_IN WHEN (IOSTRB ='0' AND RW ='0' AND DSPIS ='0') ELSE DSP_DATA_IN;
  CLR <= NOT RST;

GCLK_UUT1: IBUFG port map (I => SYS_CLK_IN, O => SYS_CLK);
GCLK_UUT2: IBUFG port map (I => DSP_CLKOUT_IN, O => DSP_CLKOUT);
rstpad : IBUF   port map (I=>RST_IN, O=>RST);
DSP_RW_UUT: IBUF port map (I => DSP_RW, O=> RW);


INSERT_MEM_CONTROL: mem_control
port map(
  MSTRB =>MSTRB,
  A19 =>A(19),
  PS =>PS,
  RW =>RW,
  DS =>DS,
  XF => XF,
  SRAM_CE =>SRAM_CE,
  SRAM_WE =>SRAM_WE,
  SRAM_OE =>SRAM_OE,
  FLASH_CE =>FLASH_CE,
  FLASH_WE =>FLASH_WE_TMP,
  FLASH_OE =>FLASH_OE
  );
FLASH_WE <= FLASH_WE_EN or FLASH_WE_TMP or XF;
end block DATA_BUS_CONNECTION;

--========================================================--
--SELECT IO SPACE
IO_SELECT:BLOCK
begin
INSERT_SYSTEM_IO: system_io