代码搜索:std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
www.eeworm.com/read/306208/13749265

vhd divider.vhd

--divider.vhd n-bit divider library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all ; use work.components.all ; entity divider is generic ( n : integer := 7 ) ; port ( c
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vhd shiftlne.vhd

--shiftlne.vhd n-bitright-to-left shift register --with parallel load and enable library ieee ; use ieee.std_logic_1164.all ; entity shiftlne is generic ( n : integer := 7 ) ; port( r : in s
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vhd geweidecord.vhd

library ieee; use ieee.std_logic_1164.all; entity geweidecord is port(key0:in std_logic; key1:in std_logic; key2:in std_logic; key3:in std_logic; ke
www.eeworm.com/read/305986/13755599

vhd 加法器源程序.vhd

------------------------------------------------------------------------ -- Single-bit adder ------------------------------------------------------------------------ library IEEE; use IEEE.std_log
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txt 加法器描述.txt

-- A Variety of Adder Styles -- download from: www.fpga.com.cn & www.pld.com.cn ------------------------------------------------------------------------ -- Single-bit adder -----------------------
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vhd 相应加法器的测试向量(test bench).vhd

-- download from: www.pld.com.cn & www.fpga.com.cn entity testbench is end; ------------------------------------------------------------------------ -- testbench for 8-bit adder ------------
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vhd pwm.vhd

-- -- pwm.vhd -- -- PWM DA converter -- -- -- -- 100k -- ___ -- sdo o--|___|--o----------o uout -- | --
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vhd memio.vhd

-- -- memio.vhd -- -- external memory and IO for JOP3 -- -- addr, wr are one cycle earlier than data -- dout one cycle after read (ior) -- -- resources on ACEX1K30-3 -- 24 LCs, xx MHz on
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readme

---------------------------------------------------------------------- -- -- -- Copyright(c) Hynix Semiconductor Inc. 2005. All rights
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vhd crc8.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for ins