代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/329134/12978784
txt 表决器源代码.txt
-- Three-input Majority Voter
-- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.
-- download from: www.pld.com.cn & w
www.eeworm.com/read/328956/12992892
vhd dds.vhd
--DDS.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
EN:IN STD_LOGIC;
RESET:IN STD_LOGIC;
www.eeworm.com/read/328956/12992990
vhd sum99.vhd
--SUM910.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SUM99 IS
PORT(K: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
CLK: IN STD_LOGIC;
EN: IN STD_L
www.eeworm.com/read/242401/13007910
vhd command.vhd
--#############################################################################
--
-- LOGIC CORE: Command module
-- MODULE NAME: command()
-- COMPANY: Altera
www.eeworm.com/read/141282/13024778
txt 加法器源程序.txt
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
www.eeworm.com/read/141282/13024780
txt 相应加法器的测试向量（test bench).txt
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/141282/13024796
txt 加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/141282/13024832
txt 一个简单的uart.txt
----------------------------------------------------------------
--
-- Copyright (c) 1992,1993,1994, Exemplar Logic Inc. All rights reserved.
--
---------------------------------------------------
www.eeworm.com/read/328300/13034851
txt weideng.txt
library iee;
use iee.std_logic_1164.all;
entity kong is
port(left,right:in std_logic;
lft,rig lr: out std_locic);
end kong
architecture kon_arc of kong is
begin
process(left,right)
va
www.eeworm.com/read/328146/13044805
vhd miniuart.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to th