weideng.txt

有用的灯

library iee;
use iee.std_logic_1164.all;
entity kong is 
	port(left,right:in std_logic;
lft,rig lr: out std_locic);
end kong 

architecture kon_arc of kong is 
begin 
	process(left,right)
variable a:std_logic_vector( 1 downto 0);
begin
a:=left & right;
case a is 
	when "00"=> lft <='0';
			rit<='0';
			lr<='0';
	when "10"=> lft<='1';
			rit<='0';
			lr<='0';
	when "01"=> rit<='1';
			lft<='0';
			lr<='0';
	when others =>rit<='1';
			lft<='1';
			lr<='1';
end case ;
end process;
end kong_arc;
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library ieee;
use ieee.std_logic_1164.all;
entity lfta is 
	port(en,clk,lr:in std_logic;
	12,11,10 : out std_logic);
end lfta;

architectrue lft_arc of lfta is 
begin 
	process(clk,en,lr)
	variable tmp:std_logic_vector(2 downto 0);
	begin
	    if lr='1' then 
		tmp:="111";
	    elsif en ='0' then
		tmp:="000";
	    elsif clk'event and clk='1' then 
		if tmp="000" then
			tmp:="001";
		elsif tmp=:"001"then
                     tmp:="010";
                elsif tmp:="010"then
                     tmp:="001";
		end if;
	    end if ;
	12<=tmp(2);
	11<=tmp(1);
	10<=tmp(0);
end process;
end lft_arc;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
library ieee;
use ieee.std_logic_1164.all;
entity rita is
	port(en clk,lr:in std_logic;
		r2,r1,r0:out std_logic);
end rita;
architecture rit_arc of rita is 
begin
	process(clk,en,lr)
	variable tmp:std_logic_vector(2 downto 0);
	begin
	 if lr='1' then 
		tmp:="111";
	elsif en='0' then 
		tmp:="000"; 
	elsif clk'event and clk='1' then
		if tmp:="000" then
		    tmp:="100";
                 elsif tmp:="100"then
                       tmp:="010";
                 elsif tmp:="010"then
                       tmp:=001;
		end if;
	end if;
	r2<=tmp(2);
	r1<=tmp(1);
	r0<=tmp(0);
end process
end rit_arc;