代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/436655/7766465
vhd bzh.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BZH IS
PORT (EN,CLK,CLR:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END;
ARCHITECTURE BHV OF BZH
www.eeworm.com/read/436472/7769545
vhd mc8051_ram.vhd
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
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vhd scan4digit.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:21:14 11/17/2008
-- Design Name:
-- Module Name: scan4digit
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vhd my_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div1024--1Hz_generator component
Port( clk: in std_logic;--from system clock(1024Hz)
f1hz : out std_logic);-- 1H
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vhd shiftrne.vhd
--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port (
r : i
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vhd divider.vhd
--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
c
www.eeworm.com/read/435744/7786021
vhd shiftlne.vhd
--shiftlne.vhd n-bitright-to-left shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftlne is
generic ( n : integer := 7 ) ;
port(
r : in s
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txt 移位寄存器.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY yiwei IS
PORT(a,l,r,clk:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END yiwei;
ARCHITECTURE rt4 OF yiwei IS
SIGNAL df0,df1,
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vhd command.vhd
--#############################################################################
--
-- LOGIC CORE: Command module
-- MODULE NAME: command()
-- COMPANY: Altera
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vhd division10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division10 is
port(lin:in std_logic_vector(9 downto 0);
clock:in std_logic;