移位寄存器.txt

这是本人在学FPEG/VHDL快速工程实践入门与提高一书时所写的相关代码。可是本人辛苦整理出来的啊。希望对大家有帮助了……

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY yiwei IS
PORT(a,l,r,clk:IN STD_LOGIC;
           q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END yiwei;

ARCHITECTURE rt4 OF yiwei IS
SIGNAL df0,df1,df2,df3:STD_LOGIC;
SIGNAL indata:STD_LOGIC_VECTOR(1 DOWNTO 0); 
BEGIN
   indata<=l&r;
   PROCESS(clk)
     BEGIN
          IF(clk'EVENT AND clk='1' ) THEN
              IF(indata="01") THEN
                  df0<=a;
                  df1<=df0;
                  df2<=df1;
                  df3<=df2;
              ELSIF(indata="10") THEN
                    df3<=a;
                    df2<=df3;
                    df1<=df2;
                    df0<=df1;
              ELSE
                  df0<=df0;
                  df1<=df1;
                  df2<=df2;
                  df3<=df3;                   

         END IF;
         END IF;
END PROCESS;

q(0)<=df0;
q(1)<=df1;
q(2)<=df2;
q(3)<=df3;

END ARCHITECTURE RT4;