代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/178935/9381809
txt program-h.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newhour is
port (carrym,reset:in std_logic;
hour1,hour2: out std_logic_vector(3 downto 0));
end newho
www.eeworm.com/read/178935/9382028
vhd newhour.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newhour is
port(carrym, reset: in std_logic;
hour1,hour2:out std_logic_vector(3 downto 0));
end newhour;
www.eeworm.com/read/374543/9397567
vhd cnt12.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT12 IS
PORT (CLK,RST,EN : IN STD_LOGIC;
CQ :OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
C0,C1,C2 :OUT STD_LOGIC );
www.eeworm.com/read/374530/9399693
vhd txmittest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmittest is
port(
tx:out std_logic;
txclkout:out std_logic;--For test send clok;
data:in std_logic_vecto
www.eeworm.com/read/374530/9399817
vhd xor32.vhd
--xor32
library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
use Ieee.std_logic_arith.all;
entity xor32 is
port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
www.eeworm.com/read/374530/9399862
vhd xor32.vhd
--xor32
library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
use Ieee.std_logic_arith.all;
entity xor32 is
port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
www.eeworm.com/read/374530/9400182
vhd division10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division10 is
port(lin:in std_logic_vector(9 downto 0);
clock:in std_logic;
www.eeworm.com/read/374530/9400243
vhd bsr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bsr is
port(din :in std_logic_vector(7 downto 0);
s:in std_logic_vector(2 downto
www.eeworm.com/read/178105/9418218
vhd counter60.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter60 is
port ( cp:in std_logic;
bin:out std_logic_vector(5 downto 0
www.eeworm.com/read/178105/9418266
vhd timer_set.vhd
----------------------------- timer_set.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
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