cnt12.vhd

双口RAM与PXI总线接口设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT12 IS
PORT (CLK,RST,EN : IN STD_LOGIC;
	CQ :OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
	C0,C1,C2 :OUT STD_LOGIC );
END CNT12;
ARCHITECTURE behav OF CNT12 IS
BEGIN
PROCESS(CLK, RST, EN)
VARIABLE CQI :STD_LOGIC_VECTOR(10 DOWNTO 0);
BEGIN
IF RST ='1' THEN CQI := (OTHERS =>'0') ; --计数器异步复位
ELSIF CLK' EVENT  AND CLK='1' THEN --检测时钟上升沿
IF EN ='1' THEN --检测是否允许计数（同步使能）
IF CQI <4000 THEN CQI := CQI +1; --允许计数, 检测是否小于4000
ELSE CQI := (OTHERS =>'0'); END IF; --大于4000，计数值清零
END IF;
END IF;
CQ <= CQI; --将计数值向端口输出 
--END PROCESS P_A;
--P_B:PROCESS(abc)
--BEGIN
CASE CQI(2 DOWNTO 0) IS --类似于真值表的CASE语句
WHEN "000" => C2<='0'; C1<='0';C0<='0' ;
WHEN "001" => C2<='0'; C1<='0';C0<='1' ;
WHEN "010" => C2<='0'; C1<='1';C0<='0' ;
WHEN "011" => C2<='0'; C1<='1';C0<='1' ;
WHEN "100" => C2<='1'; C1<='0';C0<='0' ;
WHEN "101" => C2<='1'; C1<='0';C0<='1' ;
WHEN "110" => C2<='1'; C1<='1';C0<='0' ;
WHEN "111" => C2<='1'; C1<='1';C0<='1' ;
WHEN OTHERS => NULL ;
END CASE;
END PROCESS ;
END  behav;