代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/378411/9232177
vhd spi.vhd
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is --
port( sclk:in std_logic;
cs:in std_logic;
read:in std_logic;
www.eeworm.com/read/378191/9242216
vhd nia.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nia is
port (clk, ena: in std_logic;
dn, qn: out std_logic_vector(3 downto 0);
yf: out std_
www.eeworm.com/read/181604/9244288
vhd jishu.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jishu is
port(clk1: in std_logic;
ge1,shi1: out std_logic_vector(3 downto 0);
co_sec: out std_logic
www.eeworm.com/read/181604/9244329
vhd jishu1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jishu1 is
port(clk1: in std_logic;
ge1,shi1: out std_logic_vector(3 downto 0);
co_sec: out std_logi
www.eeworm.com/read/181604/9244408
vhd jishu2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jishu2 is
port(clk1: in std_logic;
ge1,shi1: out std_logic_vector(3 downto 0));
end jishu2;
architect
www.eeworm.com/read/378183/9244985
dat tc13.dat
第10章 结构与链表
为将不同数据类型、但相互关联的一组数据,组合成一个有机整体使用,C语言提供一种称为“结构”的数据结构.
10.1 结构类型与结构变量的定义
10.2 结构变量的引用与初始化
10.3 结构数组
10.4 指向结构类型数据的指针
10.5 链表处理──结构指针的应用
10.6 共用型和枚举型
10.7 定义已有类型的别名
...
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vhd serial_generatedinstance.vhd
--------------------------------------------------
-- Model : 8051 Behavioral Model,
-- VHDL Entity mc8051.serial.generatedInstance
--
-- Author : Michael Mayer (
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vhd my_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div1024--1Hz_generator component
Port( clk: in std_logic;--from system clock(1024Hz)
f1hz : out std_logic);-- 1H
www.eeworm.com/read/377553/9271614
vhd shiftrne.vhd
--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port (
r : i
www.eeworm.com/read/377553/9271636
vhd divider.vhd
--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
c